IP Library › Granted Patent US 8,916,909
Granted Patent B2
US 8,916,909 · App. 13/413,315 · Granted Dec 23, 2014

Semiconductor device and method for fabricating a semiconductor device

Inventors: Franz Hirler (Isen, DE); Andreas Meiser (Sauerlach, DE)
Assignee: Infineon Technologies Austria AG
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Quick Facts
Patent No.
US 8,916,909
App. No.
13/413,315
Granted
Dec 23, 2014
Kind
B2
Abstract

A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

Claims (18)

1. A semiconductor device, comprising:

a body comprising:

a first portion comprising a first semiconductor material having a first bandgap;

a second portion comprising a second semiconductor material having a second bandgap, the second bandgap being different from the first bandap; and

the first portion and the second portion being coplanar and dielectrically insulated from one another; and

wherein the body is disposed on a substrate with the first and second portions being laterally adjacent to one another on the substrate, wherein the substrate includes a first region and a second region laterally adjacent to one another, the first region below the first portion and comprising a first substrate material, and the second region below the second portion and comprising a second substrate material which is different from the first substrate material.

2. The semiconductor device according to claim 1 , wherein the first portion comprises a HEMT structure.

3. The semiconductor device according to claim 1 , wherein the second portion comprises a CMOS device.

4. The semiconductor device according to claim 1 , wherein the first portion comprises a III-V semiconductor material.

5. The semiconductor device according to claim 1 , wherein the first portion comprises a GaN layer, an AlGaN layer arranged on the GaN layer and a gate electrode positioned on the AlGaN layer.

6. The semiconductor device according to claim 1 , wherein the second portion comprises <100> silicon.

7. The semiconductor device according to claim 1 , further comprising a dielectric barrie arranged in an interface between the first portion and the second portion.

8. The semiconductor device according to claim 1 , further comprising a <111> silicon layer positioned adjacent the second portion.

9. The semiconductor device according to claim 8 , further comprising a dielectric positioned adjacent the first portion.

10. The semiconductor device according to claim 1 , further comprising a dielectric layer positioned adjacent the first portion and the second portion.

11. The semiconductor device according to claim 1 , wherein the second portion comprises <100> silicon, a <111> silicon layer is positioned adjacent the second portion and an oxide layer is arranged between the <111> silicon and the <100> silicon.

12. The semiconductor device according to claim 1 , further comprising a re-wiring structure.

13. The semiconductor device of claim 1 , wherein the first substrate material comprises an insulating material, such as an oxide, and the second substrate material comprises a silicon material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2012
From: HIRLER, FRANZ; MEISER, ANDREAS
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 028242/0090 →
Continuity (1)
Related Publication 20130234145A1 · Sep 12, 2013