Semiconductor device having delay line
Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.
1. A semiconductor device comprising:
a delay line delaying a first internal clock signal to generate a second internal clock signal;
a replica circuit that generates a replica clock signal based on the second internal clock signal;
a phase determination circuit that generates a phase determination signal based on phases of the first internal clock signal and the replica clock signal; and
a counter circuit that updates a count value thereof based on the phase determination signal,
wherein the delay line includes a plurality of one-shot pulse generation circuits connected in series, and the count value defines a pulse width of a one-shot pulse generated by each of the one-shot pulse generation circuits.
2. The semiconductor device as claimed in claim 1 , wherein
the delay line includes first and second delay lines each includes the plurality of one-shot pulse generation circuits,
each of the plurality of one-shot pulse generation circuits included in the first delay line generates the one-shot pulse based on a rising edge of the first internal clock signal,
each of the plurality of one-shot pulse generation circuits included in the second delay line generates the one-shot pulse based on a falling edge of the first internal clock signal, and
the semiconductor device further comprises a mixer circuit that generates the second internal clock signal by synthesizing output signals from the first and second delay lines.
3. The semiconductor device as claimed in claim 1 , further comprising a duty-cycle correction circuit that adjusts a duty cycle of the second internal clock signal output from the delay fine to substantially 50%.
4. The semiconductor device as claimed in claim 1 , wherein
each of the one-shot pulse generation circuits includes a variable delay circuit,
each of the one-shot pulse generation circuits specifies a starting edge of a one-shot pulse based on one of a rising edge and a falling edge of an input signal, supplied thereto that has bypassed the variable delay circuit, and
each of the one-shot pulse generation circuits specifies an end edge of a one-shot pulse based on the one of a rising edge and a falling edge of the input signal that has passed through the variable delay circuit.
5. The semiconductor device as claimed in claim 1 , further comprising an output buffer circuit that outputs data to outside synchronously with the second internal clock signal,
wherein the replica circuit is substantially identical in characteristics to the output buffer circuit.
6. A method of operating a semiconductor device comprising:
delaying a first internal clock signal on a delay line to generate a second internal clock signal;
generating a replica clock signal based on the second internal clock signal;
generating a phase determination signal based on phases of the first internal clock signal and the replica clock signal; and
updating a count value thereof based on the phase determination signal,
wherein the delay line includes a plurality of one-shot pulse generation circuits connected in series, and the count value defines a pulse width of a one-shot pulse generated by each of the one-shot pulse generation circuits.
7. The method of operating a semiconductor device as claimed in claim 6 , wherein
the delay line includes first and second delay lines each including the plurality of one-shot pulse generation circuits,
generating, via each of the plurality of one-shot pulse generation circuits included in the first delay line, the one-shot pulse based on a rising edge of the first internal clock signal,
generating, via each of the plurality of one-shot pulse generation circuits included in the second delay line, the one-shot pulse based on a falling edge of the first internal clock signal, and
generating the second internal clock signal by synthesizing output signals from the first and second delay lines.
8. The method of operating a semiconductor device as claimed in claim 6 , further comprising adjusting a duly cycle of the second internal clock signal output from the delay line to substantially 50%.
9. The method of operating a semiconductor device as claimed in claim 6 , wherein
each of the one-shut pulse generation circuits includes a variable delay circuit,
specifying, via each of the one-shot pulse generation circuits, a starting edge of a one-shot pulse based on one of a rising edge and a falling edge of an input signal supplied thereto that has bypassed the variable delay circuit, and
specifying, via each of the one-shot pulse generation circuits, an end edge of a one-shot pulse based on the one of a rising edge and a falling edge of the input signal that has passed through the variable delay circuit.
10. The method of operating a semiconductor device as claimed in claim 6 , further comprising:
outputting, via an output buffer circuit, data to outside synchronously with the second internal clock signal,
wherein a replica circuit that generates a replica clock signal based on the second internal clock signal is substantially identical in characteristics to the output buffer circuit.