IP Library › Granted Patent US 8,917,337
Granted Patent B2
US 8,917,337 · App. 13/523,137 · Granted Dec 23, 2014

AD conversion circuit and imaging apparatus

Inventor: Yoshio Hagihara (Tokyo, JP)
Assignee: Olympus Corporation
H03M1/48H04N5/378H03M1/123H03M1/56
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,917,337
App. No.
13/523,137
Granted
Dec 23, 2014
Kind
B2
Abstract

A ramp section generates a reference signal. A comparison section compares an analog signal to the reference signal, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A main count section performs a count operation and outputs a count value. A latch section latches a second count value at a second timing related to the end of the comparison process corresponding to a second analog signal after latching a first count value at a first timing related to the end of the comparison process corresponding to a first analog signal. A column count section sequentially counts values of bits constituting the second count value retained in the latch section after an initial value has been set on the basis of values of bits constituting the first count value retained in the latch section.

Claims (25)

1. An AD conversion circuit comprising:

a reference signal generation section configured to generate a reference signal that increases or decreases with the passage of time;

a comparison section configured to compare an analog signal to be subjected to AD conversion output from a pixel of an image apparatus to the reference signal, and configured to terminate a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal;

a first count section configured to perform a count operation and outputting a count value;

a latch section configured to latch a second count value at a second timing related to an end of the comparison process corresponding to a second analog signal after latching a first count value at a first timing related to an end of the comparison process corresponding to a first analog signal; and

a second count section configured to sequentially count values of bits constituting the second count value retained in the latch section after an initial value has been set in the second count section on the basis of values of bits constituting the first count value retained in the latch section,

wherein digital data corresponding to a difference between the first analog signal and the second analog signal is output, and

the latch section and the second count section are arranged for every column or every plurality of columns of a pixel array of the imaging apparatus.

2. The AD conversion circuit according to claim 1 , wherein the initial value is an inversion count value obtained by inverting the values of the bits constituting the first count value.

3. The AD conversion circuit according to claim 1 , wherein the initial value is an inversion count value obtained by further inverting a third count value after the third count value has been obtained by sequentially counting the values of the bits constituting the first count value.

4. The AD conversion circuit according to claim 1 , wherein:

a count mode of the first count section is a count-up mode and a count-down mode, and

the first count value is a count value counted in one of the count-up mode and the count-down mode, and the second count value is a count value counted in the other of the count-up mode and the count-down mode.

5. An imaging apparatus comprising:

an imaging section in which a plurality of pixels having photoelectric conversion elements are arranged to output a signal corresponding to a reset level as a first analog signal and output a signal corresponding to an amount of an incident electromagnetic wave as a second analog signal; and

the AD conversion circuit according to claim 1 .

6. An imaging apparatus comprising:

an imaging section in which a plurality of pixels having photoelectric conversion elements are arranged to output a signal corresponding to a reset level as a first analog signal and output a signal corresponding to an amount of an incident electromagnetic wave as a second analog signal; and

the AD conversion circuit according to claim 2 .

7. An imaging apparatus comprising:

an imaging section in which a plurality of pixels having photoelectric conversion elements are arranged to output a signal corresponding to a reset level as a first analog signal and output a signal corresponding to an amount of an incident electromagnetic wave as a second analog signal; and

the AD conversion circuit according to claim 3 .

8. An imaging apparatus comprising:

an imaging section in which a plurality of pixels having photoelectric conversion elements are arranged to output a signal corresponding to a reset level as a first analog signal and output a signal corresponding to an amount of an incident electromagnetic wave as a second analog signal; and

the AD conversion circuit according to claim 4 .

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 27, 2016
From: OLYMPUS CORPORATION
To: OLYMPUS CORPORATION
Reel/Frame 039344/0502 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2012
From: HAGIHARA, YOSHIO
To: OLYMPUS CORPORATION
Reel/Frame 028377/0776 →
Priority Claims (1)
JP 2011-132196 · Jun 14, 2011 · national
Continuity (1)
Related Publication 20120320243A1 · Dec 20, 2012