IP Library Granted Patent US 8,921,921
Granted Patent B2
US 8,921,921 · App. 13/717,145 · Granted Dec 30, 2014

Nonvolatile memory device and method for fabricating the same

Inventor: Jung-Ryul Ahn (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L29/792H01L29/66666H01L27/1157H01L27/11582H01L29/66833H01L29/7926
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Quick Facts
Patent No.
US 8,921,921
App. No.
13/717,145
Granted
Dec 30, 2014
Kind
B2
Abstract

A nonvolatile memory device includes a stacked structure disposed over a substrate and having a plurality of interlayer dielectric layers and conductive layers that are alternately stacked, a plurality of holes formed to pass through the stacked structure to expose the substrate, a first memory layer and a second memory layer formed separately in a circumference of each hole, and a first channel layer and a second channel layer formed respectively on the first and second memory layers.

Claims (40)

1. A nonvolatile memory device comprising:

a stacked structure disposed over a substrate and having a plurality of interlayer dielectric layers and conductive layers that are alternately stacked;

a plurality of holes formed to pass through the stacked structure to expose the substrate;

a first memory layer and a second memory layer formed separately in a circumference of each hole; and

first and second channel layers formed respectively over the first and second memory layers.

2. The nonvolatile memory device of claim 1 , wherein the first memory layer and the second memory layer face each other, and

the first channel layer and second channel layer face each other.

3. The nonvolatile memory device of claim 1 , wherein each of the first memory layer and second memory layer comprises a charge blocking layer, a charge storing layer, and a tunnel insulating layer, which are sequentially arranged from a side close to the conductive layer.

4. The nonvolatile memory device of claim 1 , further comprising:

a plurality of trenches formed through the stacked structure; and

an insulating material buried in each of the trenches,

wherein each of the trenches overlaps one edge of one hole and the other edge of another hole adjacent to the one hole, in a first direction, and

the first memory layer and second memory layer and the first channel layer and second channel layer are disposed in a circumference of the hole, which are not overlapped with the trench.

5. The nonvolatile memory device of claim 4 , wherein the hole has an elliptical shape of which the diameter in the first direction is larger than the diameter in a second direction crossing the first direction.

6. A method for fabricating a nonvolatile memory device, comprising:

forming a stacked structure in which a plurality of interlayer dielectric layers and conductive layers are alternatively stacked over a substrate;

forming a plurality of holes formed to pass through the stacked structure to expose the substrate;

forming a memory layer in a circumference of each of the holes;

forming a channel layer on the memory layer; and

separating the memory layer and the channel layer into two or more parts in the hole by partially removing the memory layer and the channel layer.

7. The nonvolatile memory device of claim 6 , wherein the separating the memory layer and the channel layer comprises:

forming a mask pattern having a plurality of openings to expose the memory layer and the channel layer in a first direction; and

etching the memory layer and the channel layer exposed through the openings, using the mask pattern as an etch mask.

8. The nonvolatile memory device of claim 7 , wherein each of the openings simultaneously exposes the memory layer and the channel layer at one edge of one hole and the memory layer and the channel layer at the other edge of another hole adjacent to the one hole, in the first direction.

9. The nonvolatile memory device of claim 7 , wherein the hole has an elliptical shape of which the diameter in the first direction is larger than the diameter in a second direction crossing the first direction.

10. The nonvolatile memory device of claim 7 , further comprising burying an insulating material in the etched region, after etching the memory layer and the channel layer.

11. A method for fabricating a nonvolatile memory device, comprising:

forming a stacked structure in which a plurality of interlayer dielectric layers and sacrifice layers are alternately stacked over a substrate;

forming a plurality of holes formed to pass through the stacked structure to expose the substrate;

forming a memory layer in a circumference of each of the holes;

forming a channel layer on the memory layer;

separating the memory layer and the channel layer into two or more parts in the hole by partially removing the memory layer and the channel layer;

removing the sacrifice layers; and

forming a plurality of conductive layers by burying a conductive material in spaces formed by removing the sacrifice layers.

12. The nonvolatile memory device of claim 11 , wherein separating the memory layer and the channel layer comprises:

forming a mask pattern having a plurality of openings to expose the memory layer and the channel layer in a first direction; and

etching the memory layer and the channel layer exposed through the openings, using the mask pattern as an etch mask.

13. The nonvolatile memory device of claim 12 , wherein each of the openings simultaneously exposes the memory layer and the channel layer at one edge of one hole and the memory layer and the channel layer at the other edge of another hole adjacent to the one edge, in the first direction.

14. The nonvolatile memory device of claim 12 , wherein the hole has an elliptical shape of which the diameter in the first direction is larger than the diameter in a second direction crossing the first direction.

15. The nonvolatile memory device of claim 12 , further comprising burying an insulating material in the etched region, after etching the memory layer and the channel layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2012
From: AHN, JUNG-RYUL
To: SK HYNIX INC.
Reel/Frame 029483/0747 →
Priority Claims (1)
KR 10-2012-0084753 · Aug 2, 2012 · national
Continuity (1)
Related Publication 20140035023A1 · Feb 6, 2014