Chip package and fabrication method thereof
The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.
1. A chip package, comprising:
a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region;
a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and
a plurality of heavily doped regions isolated from one another, underlying and electrically connected and in direct physical contact to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.
2. The chip package as claimed in claim 1 , wherein the chip package further comprises: a plurality of conductive connections underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily doped regions.
3. The chip package as claimed in claim 1 , wherein the first surface is below the second surface, a semiconductor device is on the first surface, and the second surface is a light receiving surface.
4. The chip package as claimed in claim 1 , wherein the carrier substrate is a silicon-on-insulator substrate.
5. The chip package as claimed in claim 1 , further comprising a packaging layer bonded to the semiconductor substrate.
6. The chip package as claimed in claim 5 , further comprising a spacer disposed between packaging layer and the semiconductor substrate and defining a cavity between the packaging layer and the semiconductor substrate.
7. A method for fabricating a chip package, comprising:
providing a semiconductor wafer having opposite first and second surfaces, wherein the semiconductor wafer comprises at least one bond pad region, at least one device region, and a plurality of conductive pad structures disposed on the bond pad region at the first surface; and
forming a plurality of heavily doped regions underlying the conductive pad structures, wherein the heavily doped regions are isolated from one another and electrically connected and in direct physical contact to the conductive pad structures, wherein the heavily doped regions are formed in a carrier substrate; and bonding the carrier substrate to the first surface of the semiconductor wafer.
8. The method as claimed in claim 7 , further comprising: forming a plurality of conductive connections underlying the heavily doped regions, wherein the conductive connections are electrically connected to the conductive pad structures through the heavily doped regions.
9. The method as claimed in claim 7 , wherein the first surface is below the second surface, a semiconductor device is on the first surface, and the second surface is a light receiving surface.
10. The method as claimed in claim 7 , wherein the carrier substrate is a silicon-on-insulator substrate.
11. The method as claimed in claim 7 , further comprising forming an insulating wall to isolate the heavily doped regions from one another, wherein the step of forming the insulating wall comprises:
forming a plurality of openings from a first surface of the carrier substrate;
forming an insulating layer in the openings of the carrier substrate; and
polishing the carrier substrate from a second surface opposite to the first surface of the carrier substrate, to thereby form the insulating wall to isolate the heavily doped regions.
12. The method as claimed in claim 11 , further comprising: bonding a packaging layer to the semiconductor wafer, wherein the step of the forming the insulating wall is performed after the bonding of the packaging layer.
13. The method as claimed in claim 7 , further comprising bonding a packaging layer to the semiconductor wafer, wherein a cavity surrounded by a spacer is formed between the packaging layer and the semiconductor wafer.
14. A method for fabricating a chip package, comprising:
providing a semiconductor wafer having opposite first and second surfaces, wherein the semiconductor wafer comprises at least one bond pad region, at least one device region, and a plurality of conductive pad structures disposed on the bond pad region at the first surface;
forming a plurality of heavily doped regions underlying the conductive pad structures, wherein the heavily doped regions are isolated from one another and electrically connected and in direct physical contact to the conductive pad structures, wherein the heavily doped regions are formed in a carrier substrate; bonding the carrier substrate to the first surface of the semiconductor wafer, wherein the first surface is below the second surface, a semiconductor device is on the first surface, and the second surface is a light receiving surface; and
bonding a packaging layer to the semiconductor wafer, wherein a cavity surrounded by a spacer is formed between the packaging layer and the semiconductor wafer.
15. The method as claimed in claim 14 , further comprising: forming a plurality of conductive connections underlying the heavily doped regions, wherein the conductive connections are electrically connected to the conductive pad structures through the heavily doped regions.
16. The method as claimed in claim 14 , wherein the heavily doped regions are formed in a carrier substrate, and the method further comprises: bonding the carrier substrate to the first surface of the semiconductor wafer, wherein the first surface is below the second surface, a semiconductor device is on the first surface, and the second surface is a light receiving surface.