IP Library Granted Patent US 8,924,645
Granted Patent B2
US 8,924,645 · App. 13/387,718 · Granted Dec 30, 2014

Data storage apparatus and methods

Inventors: Jichuan Chang (Mountain View, CA); Parthasarathy Ranganathan (San Jose, CA); David Andrew Roberts (Ann Arbor, MI); Mehul A. Shah (Santa Clara, CA); John Sontag (Santa Clara, CA)
Assignee: Hewlett-Packard Development Company, L. P.
G06F12/0893G06F12/0888
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Quick Facts
Patent No.
US 8,924,645
App. No.
13/387,718
Filed
Jan 27, 2012
Granted
Dec 30, 2014
Kind
B2
Art Unit
2139
USPC
711/118
Abstract

Data storage apparatus and methods are disclosed. A disclosed example data storage apparatus comprises a cache layer and a processor in communication with the cache layer. The processor is to dynamically enable or disable the cache layer via a cache layer enable line based on a data store access type.

Claims (22)

1. A data storage apparatus, comprising:

a cache layer;

a processor in communication with the cache layer, the processor to dynamically enable or disable the cache layer via a cache layer enable line based on a data store access type, where the data store access type is one of a read access type and a write access type; and

a read counter to track a read count of read accesses to a non-volatile data store and a write counter to track a write count of write accesses to the non-volatile data store, the read count and the write count to facilitate determining when to dynamically enable or disable the cache layer.

2. An apparatus as defined in claim 1 , wherein the cache layer enable line gates off power from the cache layer.

3. An apparatus as defined in claim 1 , further comprising a non-volatile data store in communication with the processor, the data store access type associated with a plurality of requests to access the non-volatile data store.

4. An apparatus as defined in claim 1 , wherein the processor is to dynamically enable or disable the cache layer via the cache layer enable line based on a quantity of occurrences of data store access requests of the data store access type.

5. An apparatus as defined in claim 1 , further comprising a memory controller in communication with the processor and a non-volatile data store, the processor to obtain historical access type information indicative of types of accesses to the non-volatile data store, the historical access type information to facilitate determining when to dynamically enable or disable the cache layer.

6. An apparatus as defined in claim 1 , wherein the processor is to determine when to dynamically enable or disable the cache layer based on a write-to-read ratio of the write and read counts.

7. An apparatus as defined in claim 6 , wherein the processor is to enable the cache layer when the write-to-read ratio exceeds a threshold, and the processor is to disable the cache layer when the write-to-read ratio is below the threshold.

8. An apparatus as defined in claim 1 , wherein the processor is to enable the cache layer to prevent a rate of write accesses to a non-volatile data store that exceeds a threshold.

9. An apparatus as defined in claim 8 , wherein the threshold is associated with a write endurance property of the non-volatile data store.

10. An apparatus as defined in claim 1 , wherein disabling the cache layer comprises disabling the cache layer for a plurality of subsequent accesses to a non-volatile data store before enabling the cache layer.

11. An apparatus as defined in claim 10 , wherein the subsequent accesses include single read accesses.

12. An apparatus as defined in claim 10 , wherein the subsequent accesses include at least one burst mode access.

13. A data storage apparatus, comprising:

a non-volatile data store in a package;

a local processor in the package and in communication with the non-volatile data store, the local processor and the non-volatile data store forming a flattenable non-volatile data storage system using a dynamically disableable cache layer, the local processor in communication with an external communication interface of the package to exchange communications with devices external from the package; and

a read counter to track a read count of read accesses to the non-volatile data store and a write counter to track a write count of write accesses to the non-volatile data store, the read count and the write count to facilitate determining when to dynamically enable or disable the dynamically disableable cache layer.

14. An apparatus as defined in claim 13 , wherein the local processor is to disable power delivery to the dynamically disableable cache layer to disable the dynamically disableable cache layer.

15. An apparatus as defined in claim 13 , wherein the local processor is to determine when to dynamically enable or disable the dynamically disableable cache layer based on a write-to-read ratio of the write and read counts.

16. An apparatus as defined in claim 13 , wherein the external communication interface is to communicate with different types of communication interfaces of the devices external from the package.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2012
From: CHANG, JICHUAN; RANGANATHAN, PARTHASARATHY; ROBERTS, DAVID ANDREW; SHAH, MEHUL A.; SONTAG, JOHN
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 027784/0144 →
Continuity (2)
Provisional Application 61311744 · Mar 8, 2010
Related Publication 20120131278A1 · May 24, 2012