Graphene barrier layers for interconnects and methods for forming the same
Embodiments described herein provide interconnect barrier layers and methods for forming such barriers. A dielectric body having a trench formed in a surface thereof is provided. A first layer is formed above the dielectric body within the trench. The first layer includes amorphous carbon. A second layer is formed above the first layer. The second layer includes a metal. The dielectric body, the first layer, and the second layer are heated to convert at least some of the amorphous carbon to graphene.
1. A method comprising:
providing a dielectric body having a trench formed in a surface thereof;
forming a first layer above the dielectric body within the trench, wherein the first layer comprises amorphous carbon and completely fills at least a portion of the trench;
forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the at least a portion of the trench; and
heating the dielectric body, the first layer, and the second layer to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the at least a portion of the trench,
wherein the at least a portion of the trench comprises is a second portion having a second width, the trench further comprising a first portion having a first width, wherein the second width is less than the first width, the first portion of the trench is positioned between the second portion of the trench and the surface of the dielectric body, the first layer completely fills the second portion of the trench before the heating of the dielectric body, the first layer, and the second layer, and after the heating of the dielectric body, the first layer, and the second layer, the second portion of the trench is at least partially opened.
2. The method of claim 1 , wherein a ratio of sp 2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
3. The method of claim 2 , wherein the first layer further comprises hydrogen.
4. The method of claim 1 , wherein the heating is performed at a temperature of between about 120° C. and about 450° C.
5. The method of claim 4 , wherein the second layer comprises at least one of copper, titanium, gold, or a combination thereof.
6. The method of claim 1 , wherein the dielectric body is a dielectric layer formed above a substrate.
7. The method of claim 6 , wherein the substrate further comprises a microelectronic device, wherein the dielectric layer is formed above the microelectronic device.
8. The method of claim 7 , further comprising forming a conductive body in the trench, wherein the conductive body is electrically connected to the microelectronic device.
9. The method of claim 1 , wherein the graphene forms a graphene layer, and the graphene layer conforms to the shape of the second portion of the trench.
10. A method for forming a microelectronic assembly, the method comprising:
providing a substrate having a microelectronic device, the substrate further comprising a dielectric layer formed above the microelectronic device, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width;
forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench;
forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the lower portion of the trench;
heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120° C. and about 900° C. to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and
forming a conductive body within the trench, wherein the conductive body is electrically connected to the microelectronic device, and a portion of the conductive body is positioned within the lower portion of the trench.
11. The method of claim 10 , wherein the dielectric layer, the first layer, and the second layer are heated to a temperature of between about 120° C. and about 450° C.
12. The method of claim 11 , wherein the second layer comprises at least one of copper, titanium, gold, or a combination thereof.
13. The method of claim 12 , wherein a ratio of sp 2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
14. The method of claim 13 , wherein the graphene forms a graphene layer, and the graphene layer conforms to the shape of the second portion of the trench.
15. A method for forming a microelectronic assembly, the method comprising:
providing a substrate having a transistor, the substrate further comprising a dielectric layer formed above the transistor, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width;
forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench;
forming a second layer above the first layer, wherein the second layer comprises copper, nickel, cobalt, titanium, or a combination thereof, and all of the second layer is positioned external to the lower portion of the trench;
heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120° C. and about 450° C. to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and
forming a conductive body within the trench, wherein the conductive body is electrically connected to the transistor, and a portion of the conductive body is positioned within the lower portion of the trench.
16. The method of claim 15 , wherein a ratio of sp 2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
17. The method of claim 16 , wherein the first layer further comprises hydrogen.
18. The method of claim 17 , wherein the substrate comprises a semiconductor material, glass, or a combination thereof.
19. The method of claim 18 , wherein the dielectric layer comprises silicon oxide, silicon nitride, a low-k dielectric material, of a combination thereof, and wherein the second width is about 1.7 nanometers (nm).