Dynamic deskew for bang-bang timing recovery in a communication system
Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled that iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin and voltage, the margin phase detector determines whether the sample phase is correct.
1. A method of calibrating a sampling phase adjustment of a receiver, the method comprising:
generating, by an analog-to-digital converter (ADC) of the receiver, an actual ADC value for each bit sample of a received signal, each bit sample occurring at a sample phase of the receiver;
selecting, by a phase detector of the receiver, a window of n received bit samples, n a positive integer;
if the bit window includes one or more Nyquist patterns:
enabling a bang-bang trap of the phase detector;
iteratively performing, by the bang-bang-trap, for each bit transition between a first consecutive bit and a second consecutive bit in the one or more Nyquist patterns:
sampling the received signal at a zero crossing between the first and second consecutive bits;
determining the polarity of the bit transition between the first and second consecutive bits;
determining, based on the polarity of the bit transition and the sample value at the zero crossing between the first and second consecutive bits, whether the sample phase of the bit sample for the second consecutive bit is correct; and
if the sample phase is incorrect, adjusting the sample phase of the receiver by a first predetermined amount;
if one or more Nyquist patterns are absent from the bit window:
by a margin phase detector of the receiver:
determining a target voltage margin value;
determining a voltage of a cursor bit of the selected window of bit samples;
determining, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct; and
if the sample phase is incorrect, adjusting the sample phase of the receiver by a second predetermined amount;
by a deskew module of the receiver:
based on the determining if the sample phase of the margin phase detector is correct or incorrect, incrementing a corresponding value of one of a margin phase early counter and a margin phase late counter;
based on the determining if the sample phase of the bang-bang trap is early or late, incrementing a corresponding value of one of a bang-bang phase early counter and a bang-bang phase late counter; and
determining, for the bit window, a ratio of the bang-bang phase early counter value to the bang-bang phase late counter value; and
determining, for the bit window, a ratio of the margin phase early counter value to the margin phase late counter value.
2. The method of claim 1 , further comprising:
by the bang-bang trap:
determining the sample phase is late if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 1, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 0; and
determining the sample phase is early if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 0, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 1; and
by the margin phase detector:
determining the sample phase is late if the voltage of the cursor bit is greater than the target voltage margin value; and
determining the sample phase is early if the voltage of the cursor bit is less than the target voltage margin value.
3. The method of claim 1 , further comprising:
if the bang-bang phase ratio is greater than the margin phase ratio:
reducing the sampling phase of the bang-bang trap by a predetermined step value, wherein reducing the sampling phase moves the sampling phase later in time; and
if the bang-bang phase ratio is less than the margin phase ratio:
increasing the sampling phase of the bang-bang trap by a predetermined step value, wherein increasing the sampling phase moves the sampling phase earlier in time.
4. The method of claim 3 , further comprising:
if the bang-bang phase ratio is substantially equal to the margin phase ratio:
suspending the adjusting of the sampling phase of the bang-bang trap.
5. The method of claim 3 , wherein the predetermined step value comprises one or more predetermined step sizes for adjustment of the sample phase.
6. The method of claim 1 , comprising performing the determining by the bang-bang trap and the determining by the margin phase detector substantially concurrently.
7. The method of claim 1 , further comprising:
adjusting, by the deskew module, the zero crossing sampling phase of the bang-bang trap thereby calibrating for temperature and process variation of the receiver and for sinusoidal jitter present in the received signal.
8. A non-transitory machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of calibrating a sampling phase adjustment of a receiver, the method comprising:
generating, by an analog-to-digital converter (ADC) of the receiver, an actual ADC value for each bit sample of a received signal, each bit sample occurring at a sample phase of the receiver;
selecting, by a phase detector of the receiver, a window of n received bit samples, n a positive integer;
if the bit window includes one or more Nyquist patterns:
enabling a bang-bang trap of the phase detector;
iteratively performing, by the bang-bang-trap, for each bit transition between a first consecutive bit and a second consecutive bit in the one or more Nyquist patterns:
sampling the received signal at a zero crossing between the first and second consecutive bits;
determining the polarity of the bit transition between the first and second consecutive bits;
determining, based on the polarity of the bit transition and the sample value at the zero crossing between the first and second consecutive bits, whether the sample phase of the bit sample for the second consecutive bit is correct; and
if the sample phase is incorrect, adjusting the sample phase of the receiver by a first predetermined amount;
if one or more Nyquist patterns are absent from the bit window:
by a margin phase detector of the receiver:
determining a target voltage margin value;
determining a voltage of a cursor bit of the selected window of bit samples;
determining, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct; and
if the sample phase is incorrect, adjusting the sample phase of the receiver by a second predetermined amount;
by a deskew module of the receiver:
based on the determining if the sample phase of the margin phase detector is correct or incorrect, incrementing a corresponding value of one of a margin phase early counter and a margin phase late counter;
based on the determining if the sample phase of the bang-bang trap is early or late, incrementing a corresponding value of one of a bang-bang phase early counter and a bang-bang phase late counter; and
determining, for the bit window, a ratio of the bang-bang phase early counter value to the bang-bang phase late counter value; and
determining, for the bit window, a ratio of the margin phase early counter value to the margin phase late counter value.
9. The non-transitory machine-readable medium of claim 8 , further comprising:
by the bang-bang trap:
determining the sample phase is late if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 1, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 0; and
determining the sample phase is early if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 0, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 1; and
by the margin phase detector:
determining the sample phase is late if the voltage of the cursor bit is greater than the target voltage margin value; and
determining the sample phase is early if the voltage of the cursor bit is less than the target voltage margin value.
10. The non-transitory machine-readable medium of claim 8 , further comprising:
if the bang-bang phase ratio is greater than the margin phase ratio:
reducing the sampling phase of the bang-bang trap by a predetermined step value, wherein reducing the sampling phase moves the sampling phase later in time; and
if the bang-bang phase ratio is less than the margin phase ratio:
increasing the sampling phase of the bang-bang trap by a predetermined step value, wherein increasing the sampling phase moves the sampling phase earlier in time.
11. The non-transitory machine-readable medium of claim 10 , further comprising:
if the bang-bang phase ratio is substantially equal to the margin phase ratio:
suspending the adjusting of the sampling phase of the bang-bang trap.
12. The non-transitory machine-readable medium of claim 10 , wherein the predetermined step value comprises one or more predetermined step sizes for adjustment of the sample phase.
13. The non-transitory machine-readable medium of claim 8 , comprising performing the determining by the bang-bang trap and the determining by the margin phase detector substantially concurrently.
14. The non-transitory machine-readable medium of claim 8 , further comprising:
adjusting, by the deskew module, the zero crossing sampling phase of the bang-bang trap thereby calibrating for temperature and process variation of the receiver and for sinusoidal jitter present in the received signal.
15. A communication system comprising:
a transmitting device configured to transmit a signal over a communication channel to a receiver of the communication system;
an analog-to-digital converter (ADC) of the receiver configured to generate an actual ADC value for each bit sample of the signal, each bit sample occurring at an associated sample phase of the receiver;
a phase detector of the receiver configured to:
select a window of n received bit samples, n a positive integer;
if the bit window includes one or more Nyquist patterns:
enable a bang-bang trap of the phase detector;
iteratively, for each bit transition between a first consecutive bit and a second consecutive bit in the one or more Nyquist patterns:
sample the received signal at a zero crossing between the first and second consecutive bits;
determine the polarity of the bit transition between the first and second consecutive bits;
determine, based on the polarity of the bit transition and the sample value at the zero crossing between the first and second consecutive bits, whether the sample phase of the bit sample for the second consecutive bit is correct; and
if the sample phase is incorrect, adjust the sample phase of the receiver by a first predetermined amount;
if one or more Nyquist patterns are absent from the bit window, a margin phase detector of the receiver is configured to:
determine a target voltage margin value;
determine a voltage of a cursor bit of the selected window of bit samples;
determine, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct; and
if the sample phase is incorrect, adjust the sample phase of the receiver by a second predetermined amount;
and wherein a deskew module of the receiver is configured to:
based on the determining if the sample phase of the margin phase detector is correct or incorrect, increment a corresponding value of one of a margin phase early counter and a margin phase late counter;
based on the determining if the sample phase of the bang-bang trap is early or late, increment a corresponding value of one of a bang-bang phase early counter and a bang-bang phase late counter;
determine, for the bit window, a ratio of the bang-bang phase early counter value to the bang-bang phase late counter value;
determine, for the bit window, a ratio of the margin phase early counter value to the margin phase late counter value;
if the bang-bang phase ratio is greater than the margin phase ratio:
reduce the sampling phase of the bang-bang trap by a predetermined step value, wherein reducing the sampling phase moves the sampling phase later in time; and
if the bang-bang phase ratio is less than the margin phase ratio:
increase the sampling phase of the bang-bang trap by a predetermined step value, wherein increasing the sampling phase moves the sampling phase earlier in time.
16. The communication system of claim 15 , wherein:
the bang-bang trap is further configured to:
determine the sample phase is late if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 1, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 0; and
determine the sample phase is early if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 0, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 1; and
the margin phase detector is further configured to:
determine the sample phase is late if the voltage of the cursor bit is greater than the target voltage margin value; and
determine the sample phase is early if the voltage of the cursor bit is less than the target voltage margin value.
17. The communication system of claim 15 , wherein the deskew module is further configured to:
if the bang-bang phase ratio is substantially equal to the margin phase ratio:
suspend the adjusting of the sampling phase of the bang-bang trap.
18. The communication system of claim 15 , wherein the determining by the bang-bang trap and the determining by the margin phase detector are configured to occur substantially concurrently.
19. The communication system of claim 15 , wherein the deskew module is further configured to:
adjust the zero crossing sampling phase of the bang-bang trap thereby calibrating for temperature and process variation of the receiver and for sinusoidal jitter present in the received signal.
20. A receiver comprising:
an analog-to-digital converter (ADC) configured to generate an actual ADC value for each bit sample of a received signal, each bit sample occurring at an associated sample phase of the receiver;
a phase detector configured to:
select a window of n received bit samples, n a positive integer;
if the bit window includes one or more Nyquist patterns:
enable a bang-bang trap of the phase detector;
iteratively, for each bit transition between a first consecutive bit and a second consecutive bit in the one or more Nyquist patterns:
sample the received signal at a zero crossing between the first and second consecutive bits;
determine the polarity of the bit transition between the first and second consecutive bits;
determine, based on the polarity of the bit transition and the sample value at the zero crossing between the first and second consecutive bits, whether the sample phase of the bit sample for the second consecutive bit is correct; and
if the sample phase is incorrect, adjust the sample phase of the receiver by a first predetermined amount;
if one or more Nyquist patterns are absent from the bit window, a margin phase detector of the receiver is configured to:
determine a target voltage margin value;
determine a voltage of a cursor bit of the selected window of bit samples;
determine, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct; and
if the sample phase is incorrect, adjust the sample phase of the receiver by a second predetermined amount;
and wherein a deskew module of the receiver is configured to:
based on the determining if the sample phase of the margin phase detector is correct or incorrect, increment a corresponding value of one of a margin phase early counter and a margin phase late counter;
based on the determining if the sample phase of the bang-bang trap is early or late, increment a corresponding value of one of a bang-bang phase early counter and a bang-bang phase late counter;
determine, for the bit window, a ratio of the bang-bang phase early counter value to the bang-bang phase late counter value;
determine, for the bit window, a ratio of the margin phase early counter value to the margin phase late counter value;
if the bang-bang phase ratio is greater than the margin phase ratio:
reduce the sampling phase of the bang-bang trap by a predetermined step value, wherein reducing the sampling phase moves the sampling phase later in time and if the bang-bang phase ratio is less than the margin phase ratio:
increase the sampling phase of the bang-bang trap by a predetermined step value, wherein increasing the sampling phase moves the sampling phase earlier in time.
21. The receiver of claim 20 , wherein:
the bang-bang trap is further configured to:
determine the sample phase is late if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 1, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 0; and
determine the sample phase is early if one of: (1) the bit transition polarity is 0 to 1, and the sample value at the zero crossing is equal to 0, and (2) the bit transition polarity is 1 to 0 and the sample value at the zero crossing is equal to 1; and
the margin phase detector is further configured to:
determine the sample phase is late if the voltage of the cursor bit is greater than the target voltage margin value; and
determine the sample phase is early if the voltage of the cursor bit is less than the target voltage margin value.
22. The receiver of claim 20 , wherein the deskew module is further configured to:
if the bang-bang phase ratio is substantially equal to the margin phase ratio:
suspend the adjusting of the sampling phase of the bang-bang trap.
23. The receiver of claim 20 , wherein the determining by the bang-bang trap and the determining by the margin phase detector are configured to occur substantially concurrently.
24. The receiver of claim 20 , wherein the deskew module is further configured to:
adjust the zero crossing sampling phase of the bang-bang trap thereby calibrating for temperature and process variation of the receiver and for sinusoidal jitter present in the received signal.