IP Library Granted Patent US 8,933,933
Granted Patent B2
US 8,933,933 · App. 11/430,635 · Granted Jan 13, 2015

Optimizing a graphics rendering pipeline using early Z-mode

Inventors: Mark J. French (Raleigh, NC); Emmett M. Kilgariff (San Jose, CA); Steven E. Molnar (Chapel Hill, NC); Walter R. Steiner (Flagler Beach, FL); Douglas A. Voorhies (Menlo Park, CA); Adam Clark Weitkemper (Morrisville, NC)
Assignee: NVIDIA Corporation
G06T15/405G06T15/005
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Quick Facts
Patent No.
US 8,933,933
App. No.
11/430,635
Granted
Jan 13, 2015
Kind
B2
Abstract

One embodiment of the present invention sets forth an architecture for advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for “early” Z-testing is possible or whether the Z-test function should be deferred until after shading operations for “late” Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. The same functional units are utilized in both early Z and late Z configurations.

Claims (38)

1. A configurable graphics rendering pipeline for processing graphics primitives, the graphics rendering pipeline comprising:

a setup engine configured to determine whether processing should proceed in early Z-mode or late Z-mode;

a raster engine configured to receive a geometry primitive from the setup engine and convert the geometry primitive into one or more pixel primitives;

a shader engine configured to perform shading operations on one or more samples associated with a pixel primitive;

a Z-raster operations (ZROP) unit configured to perform Z-testing on each of the samples; and

a pre-raster operations (PROP) unit configured to modify, via one or more multiplexers, a data flow path between the shader engine and the ZROP unit to support both early Z-mode and late Z-mode, wherein the PROP unit includes a Z-resolve engine that is configured in both early Z-mode and late Z-mode to discard samples that do not pass the Z-testing performed by the ZROP unit,

wherein the samples associated with the pixel primitive are processed first by the ZROP unit and the Z-resolve engine and then by the shader engine when the graphics rendering pipeline is configured for early Z-mode, and the samples are processed first by the shader engine and then by the ZROP unit and the Z-resolve engine when the graphics rendering pipeline is configured for late Z-mode.

2. The graphics rendering pipeline of claim 1 , wherein the setup engine is configured to evaluate a rendering state associated with the geometry primitive to determine whether a change from early Z-mode to late Z-mode or from late Z-mode to early Z-mode should be made.

3. The graphics rendering pipeline of claim 2 , wherein the set up engine is configured to execute a flush operation prior to switching from early Z-mode to late Z-mode or from late Z-mode to early Z-mode.

4. The graphics rendering pipeline of claim 3 , wherein the setup engine is configured to instruct the PROP unit to modify the data flow path between the shader engine and the ZROP unit to switch from early Z-mode to late Z-mode or from late Z-mode to early Z-mode.

5. The graphics rendering pipeline of claim 1 , wherein the setup engine comprising a hysteresis counter that tracks the number of geometry primitives presented to the setup engine since the graphics rendering pipeline was last configured for late Z-mode.

6. The graphics rendering pipeline of claim 1 , wherein a hysteresis count is set to a count value, and the hysteresis count is advanced each time the setup engine receives a new geometry primitive while the graphics rendering pipeline is configured for late Z-mode.

7. The graphics rendering pipeline of claim 6 , wherein the setup engine is permitted to switch the graphics rendering pipeline configuration to early Z-mode when the hysteresis count equals a trigger value.

8. A computer system configured to process graphics primitives, the computer system comprising:

a memory; and

a processing unit that includes a configurable graphics rendering pipeline having:

a setup engine configured to determine whether processing should proceed in early Z-mode or late Z-mode;

a raster engine configured to receive a geometry primitive from the setup engine and convert the geometry primitive into one or more pixel primitives;

a shader engine configured to perform shading operations on one or more samples associated with a pixel primitive;

a Z-raster operations (ZROP) unit configured to perform Z-testing on each of the samples; and

a pre-raster operations (PROP) unit configured to modify, via one or more multiplexers, a data flow path between the shader engine and the ZROP unit to support both early Z-mode and late Z-mode, wherein the PROP unit includes a Z-resolve engine that is configured in both early Z-mode and late Z-mode to discard samples that do not pass the Z-testing performed by the ZROP unit,

wherein the samples associated with the pixel primitive are processed first by the ZROP unit and the Z-resolve engine and then by the shader engine when the graphics rendering pipeline is configured for early Z-mode, and the samples are processed first by the shader engine and then by the ZROP unit and the Z-resolve engine when the graphics rendering pipeline is configured for late Z-mode.

9. The computing system of claim 8 , wherein the setup engine is configured to evaluate a rendering state associated with the geometry primitive to determine whether a change from early Z-mode to late Z-mode or from late Z-mode to early Z-mode should be made.

10. The computing system of claim 9 , wherein the set up engine is configured to execute a flush operation prior to switching from early Z-mode to late Z-mode or from late Z-mode to early Z-mode.

11. The computing system of claim 10 , wherein the setup engine is configured to instruct the PROP unit to modify the data flow path between the shader engine and the ZROP unit to switch from early Z-mode to late Z-mode or from late Z-mode to early Z-mode.

12. The computing system of claim 8 , wherein the setup engine comprises a hysteresis counter that tracks the number of geometry primitives presented to the setup engine since the graphics rendering pipeline was last configured for late Z-mode.

13. The computing system of claim 8 , wherein a hysteresis count is set to a count value, and the hysteresis count is advanced each time the setup engine receives a new geometry primitive while the graphics rendering pipeline is configured for late Z-mode.

14. The computing system of claim 13 , wherein the setup engine is permitted to switch the graphics rendering pipeline configuration to early Z-mode when the hysteresis count equals a trigger value.

15. A method for switching the configuration of a graphics rendering pipeline between early Z-mode and late Z-mode, the method comprising:

receiving a geometry primitive;

determining whether the graphics rendering pipeline is configured for early Z-mode or for late Z-mode;

determining whether to switch, via one or more multiplexers included in a pre-raster operations (PROP) unit, the configuration of the graphics rendering pipeline from early Z-mode to late Z-mode or from late Z-mode to early Z-mode, wherein the PROP unit further includes a Z-resolve engine that is configured in both early Z-mode and late Z-mode to discard samples that do not pass the Z-testing performed by a Z-raster operations (ZROP) unit; and

executing a flush operation to complete in-progress work in the graphics rendering pipeline, if the configuration of the graphics rendering pipeline is to be switched.

16. The method of claim 15 , further comprising the step of advancing a hysteresis count upon receiving the geometry primitive, if the graphics rendering pipeline is determined to be configured for late Z-mode.

17. The method of claim 16 , wherein the step of determining whether to switch the configuration of the graphics rendering pipeline comprises determining whether the hysteresis count is equal to a trigger value, if the graphics rendering pipeline is determined to be configured for late Z-mode.

18. The method of claim 15 , further comprising the step of switching, via the one or more multiplexers, the configuration of the graphics rendering pipeline to early Z-mode by modifying a data flow path through the graphics rendering pipeline so that pixel primitives are transmitted to the ZROP unit and the Z-resolve engine before being transmitted to a shader engine.

19. The method of claim 15 , wherein the step of determining whether to switch the configuration of the graphics rendering pipeline comprises evaluating a rendering state associated with the geometry primitive.

20. The method of claim 15 , wherein the graphics rendering pipeline is configured for early Z-mode, and further comprising the step of switching the configuration to late Z-mode by modifying a data flow path through the graphics rendering pipeline so that pixel primitives are transmitted to a shader engine before being transmitted to the ZROP unit and the Z-resolve engine.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2006
From: FRENCH, MARK J.; KILGARIFF, EMMETT M.; MOLNAR, STEVEN E.; STEINER, WALTER R.; VOORHIES, DOUGLAS A; WEITKEMPER, ADAM CLARK
To: NVIDIA CORPORATION
Reel/Frame 017885/0147 →
Continuity (1)
Related Publication 20070257905A1 · Nov 8, 2007