Echo prevention circuit having signal subtracter feature
View Patent ↗An echo prevention circuit comprises an input terminal to which a first input signal is input; a first FIR filter into which the first input signal is input through the input terminal; a second FIR filter into which the first input signal is input at the same time as into the first FIR filter; an input/output terminal to which an output signal of the first FIR filter is output or a second input signal is input; a subtracter that subtracts an output signal of the second FIR filter from a combined signal of the output signal of the first FIR filter and the second input signal; and an output terminal to which an output signal of the subtracter is output. The first and the second FIR filters have such filter coefficients that the output signal through the output terminal has only the output signal from the first FIR filter removed.
1. An echo prevention circuit comprising:
a first AD converter configured to convert a voice signal into a first digital signal;
an input terminal to which the first digital signal is input;
a first FIR filter configured to process the first digital signal with a filter coefficient set therein and output a second digital signal;
a second FIR filter configured to process the first digital signal, that is input at the same time as into the first FIR filter, with a filter coefficient set therein and output a third digital signal;
a first DA converter configured to convert the second digital signal into a first analog signal;
a second DA converter configured to convert the third digital signal into a second analog signal;
an input/output terminal to which the first analog signal is output and a third analog signal is input;
a subtracter configured to subtract the second analog signal from a combined signal of the first analog signal and the third analog signal and output a fourth analog signal;
a second AD converter configured to convert the fourth analog signal into a fourth digital signal;
an output terminal to which the fourth digital signal is output; and
a third DA converter configured to convert the fourth digital signal from the output terminal into a fifth analog signal;
wherein the first FIR filter coefficients and the second FIR filter coefficients are set such that the fifth analog signal from the output terminal has only the first analog signal from the first DA converter removed or reduced.
2. The echo prevention circuit according to claim 1 , wherein the filter coefficients of the second FIR filter are first impulse response of from the output of the first FIR filter to the output of the subtracter, and the filter coefficients of the first FIR filter are the inverse in phase of second impulse response of from the output of the second FIR filter to the output of the subtracter.
3. The echo prevention circuit according to claim 1 , wherein the filter coefficients of the second FIR filter are the inverse in phase of first impulse response of from the output of the first FIR filter to the output of the subtracter, and the filter coefficients of the first FIR filter are second impulse response of from the output of the second FIR filter to the output of the subtracter.
4. The echo prevention circuit according to claim 2 ,
wherein the first analog signal of the first DA converter, output through the input/output terminal, can be reflected by an earphone microphone that converts the first analog signal into voice and outputs and that converts inputted voice into the third analog signal and outputs, and be input to the input/output terminal, and
wherein the first impulse response is impulse response of from the output of the first FIR filter through the earphone microphone to the output of the subtracter for a state where the earphone microphone is connected to the input/output terminal.
5. The echo prevention circuit according to claim 2 ,
wherein the first impulse response is impulse response of from the first DA converter to the second AD converter, and the second impulse response is impulse response of from the second DA converter to the second AD converter.
6. The echo prevention circuit according to claim 5 , wherein the first impulse response is impulse response of from the first DA converter through the earphone microphone to the second AD converter for a state where an earphone microphone that converts the first analog signal of the first DA converter into voice and outputs and that converts inputted voice into the third analog signal and outputs is connected to the input/output terminal.
7. The echo prevention circuit according to claim 5 , further comprising:
an amplifier in between the output of the subtracter and the input of the second AD converter that amplifies the fourth analog signal,
wherein the first impulse response is a product of impulse response of from the first DA converter to the subtracter and impulse response of from the subtracter to the second AD converter, and the second impulse response is a product of impulse response of from the second DA converter to the subtracter and impulse response of from the subtracter to the second AD converter.
8. The echo prevention circuit according to claim 7 , wherein the first impulse response is a product of impulse response of from the first DA converter through the earphone microphone to the subtracter and impulse response of from the subtracter to the second AD converter for a state where an earphone microphone that converts the first analog signal of the first DA converter into voice and outputs and that converts inputted voice into the third analog signal and outputs is connected to the input/output terminal.
9. The echo prevention circuit according to claim 5 , further comprising:
a filter coefficient setting unit that sets the filter coefficients of the second FIR filter based on the first impulse response and sets the filter coefficients of the first FIR filter based on the second impulse response.
10. The echo prevention circuit according to claim 1 , wherein the subtracter is a differential amplifier having the combined signal of the first analog signal and the third analog signal, and the second analog signal inputted thereto.
11. The echo prevention circuit according to claim 1 , wherein the subtracter has:
an inverting circuit that inverts the second analog signal;
a gain phase adjusting circuit that adjusts gain and phase of an output signal of the inverting circuit; and
an adder that adds the combined signal of the first analog signal and the third analog signal, and an output signal of the gain phase adjusting circuit.
12. The echo prevention circuit according to claim 4 , wherein the first impulse response is one for a state where the earphone microphone is attached to an ear.
13. A digital signal processing circuit comprising:
a first input terminal to which a voice signal is input;
a first AD converter configured to convert the voice signal into a first digital signal;
a first FIR filter configured to process the first digital signal with a filter coefficient set therein and output a second digital signal;
a second FIR filter configured to process the first digital signal, that is input at the same time as into the first FIR filter, with a filter coefficient set therein and output a third digital signal;
a first DA converter configured to convert the second digital signal into a first analog signal;
a second DA converter configured to convert the third digital signal into a second analog signal;
a first output terminal to which the first analog signal is output;
a second output terminal to which the second analog signal is output;
a subtracter configured to subtract the second analog signal from a combined signal of the first analog signal and a third analog signal on an input/output signal common line and output a fourth analog signal;
a second input terminal to which the fourth signal is input;
a second AD converter configured to convert the fourth analog signal into a fourth digital signal;
a third DA converter configured to convert the fourth digital signal into a fifth analog signal; and
a third output terminal to which the fifth analog signal is output,
wherein the first FIR filter coefficients and the second FIR filter coefficients are set such that the fifth analog signal from the third output terminal has only the first analog signal from the first DA converter removed or reduced.
14. The digital signal processing circuit according to claim 13 , wherein the filter coefficients of the second FIR filter are first impulse response of from the first DA converter, to the second AD converter, and
the filter coefficients of the first FIR filter are the inverse in phase of second impulse response of from the second DA converter, to the second AD converter.
15. The digital signal processing circuit according to claim 13 , wherein the filter coefficients of the second FIR filter are the inverse in phase of first impulse response of from the first DA converter, to the second AD converter, and
the filter coefficients of the first FIR filter are second impulse response of from the second DA converter, to the second AD converter.
16. The digital signal processing circuit according to claim 14 , wherein the first impulse response is impulse response of from the first DA converter, through an earphone microphone that converts the first analog signal of the first DA converter into voice and outputs and that converts inputted voice into the third analog signal and outputs, to the second AD converter.
17. The digital signal processing circuit according to claim 14 ,
wherein the first impulse response is impulse response of from the first DA converter to the second AD converter, and the second impulse response is impulse response of from the second DA converter to the second AD converter.
18. The digital signal processing circuit according to claim 17 , wherein the first impulse response is impulse response of from the first DA converter through an earphone microphone that converts the first analog signal into voice and outputs and that converts inputted voice into the third analog signal and outputs, to the second AD converter.
19. The digital signal processing circuit according to claim 14 , further comprising:
a filter coefficient setting unit that sets the filter coefficients of the second FIR filter based on the first impulse response and sets the filter coefficients of the first FIR filter based on the second impulse response.
20. The digital signal processing circuit according to claim 16 , wherein the first impulse response is one for a state where the earphone microphone is attached to an ear.
21. A method of setting filter coefficients of an echo prevention circuit, the circuit comprising:
a first AD converter configured to convert a voice signal into a first digital signal;
an input terminal to which the first digital signal is input;
a first FIR filter configured to process the first digital signal with a filter coefficient set therein and output a second digital signal;
a second FIR filter configured to process the first digital signal, that is input at the same time as into the first FIR filter, with a filter coefficient set therein and output a third digital signal;
a first DA converter configured to convert the second digital signal into a first analog signal;
a second DA converter configured to convert the third digital signal into a second analog signal;
an input/output terminal to which the first analog signal is output and a third analog signal is input;
a subtracter configured to subtract the second analog signal from a combined signal of the first analog signal and the third analog signal and output a fourth analog signal;
a second AD converter configured to convert the fourth analog signal into a fourth digital signal;
an output terminal the fourth digital signal is output, and
a third DA converter configured to convert the fourth digital signal from the output terminal into a fifth analog signal;
the method comprising setting the first FIR filter coefficients and the second FIR filter coefficients such that the fifth analog signal from the output terminal has only the first analog signal from the first DA converter removed or reduced.
22. The method of setting filter coefficients of the echo prevention circuit according to claim 21 , comprising:
setting the filter coefficients of the second FIR filter to first impulse response of from the output of the first FIR filter to the output of the subtracter; and
setting the filter coefficients of the first FIR filter to the inverse in phase of second impulse response of from the output of the second FIR filter to the output of the subtracter.
23. The method of setting filter coefficients of the echo prevention circuit according to claim 21 , comprising:
setting the filter coefficients of the second FIR filter to the inverse in phase of first impulse response of from the output of the first FIR filter to the output of the subtracter; and
setting the filter coefficients of the first FIR filter to second impulse response of from the output of the second FIR filter to the output of the subtracter.
24. The method of setting filter coefficients of the echo prevention circuit according to claim 22 ,
wherein the first analog signal of the first DA converter, output through the input/output terminal, can be reflected by an earphone microphone that converts the first analog signal into voice and outputs and that converts inputted voice into the third analog signal and outputs, and be input to the input/output terminal, and
wherein the first impulse response is impulse response of from the output of the first FIR filter through the earphone microphone to the output of the subtracter for a state where the earphone microphone is connected to the input/output terminal.
25. The method of setting filter coefficients of the echo prevention circuit according to claim 24 , wherein the first impulse response is one for a state where the earphone microphone is attached to an ear.
26. The method of setting filter coefficients of the echo prevention circuit according to claim 21 , further comprising:
acquiring first impulse response of from the first analog signal of the first DA converter to the output of the subtracter;
acquiring second impulse response of from the second analog signal of the second DA converter to the output of the subtracter;
setting the filter coefficients of the first FIR filter to the inverse in phase of the second impulse response; and
setting the filter coefficients of the second FIR filter to the first impulse response.
27. The method of setting filter coefficients of the echo prevention circuit according to claim 21 , further comprising:
acquiring first impulse response of from the first analog signal of the first DA converter to the output of the subtracter;
acquiring second impulse response of from the second analog signal of the second DA converter to the output of the subtracter;
setting the filter coefficients of the first FIR filter to the second impulse response; and
setting the filter coefficients of the second FIR filter to the inverse in phase of the first impulse response.
28. The method of setting filter coefficients of the echo prevention circuit according to claim 26 , wherein the first impulse response is impulse response of from the first analog signal of the first DA converter through the earphone microphone to the output of the subtracter for a state where an earphone microphone that converts the first analog signal into voice and that converts inputted voice into the third analog signal is connected to the input/output terminal.
29. The method of setting filter coefficients of the echo prevention circuit according to claim 28 , wherein the first impulse response is one for a state where the earphone microphone is attached to an ear.
30. A method of setting filter coefficients of a digital signal processing circuit, the circuit comprising:
a first input terminal to which a voice signal is input;
a first AD converter configured to convert the voice signal into a first digital signal;
a first FIR filter configured to process the first digital signal with a filter coefficient set therein and output a second digital signal;
a second FIR filter configured to process the first digital signal, that is input at the same time as into the first FIR filter, with a filter coefficient set therein and output a third digital signal;
a first DA converter configured to convert the second digital signal into a first analog signal;
a second DA converter configured to convert the third digital signal into a second analog signal;
a first output terminal to which the first analog signal is output;
a second output terminal to which the second analog signal is output;
a subtracter configured to subtract the second analog signal from a combined signal of the first analog signal and a third analog signal on an input/output signal common line and output a fourth analog signal;
a second input terminal to which the fourth signal is input;
a second AD converter configured to convert the fourth analog signal into a fourth digital signal;
a third DA converter configured to convert the fourth digital signal into a fifth analog signal; and
a third output terminal to which the fifth analog signal is output,
the method comprising setting the first FIR filter coefficients and the second FIR filter coefficients such that the fifth analog signal from the third output terminal has only the first analog signal from the first DA converter removed or reduced.
31. The method of setting filter coefficients of the digital signal processing circuit according to claim 30 , comprising:
setting the filter coefficients of the second FIR filter to first impulse response of from the first DA converter, to the second AD converter; and
setting the filter coefficients of the first FIR filter to the inverse in phase of second impulse response of from the second DA converter, to the second AD converter.
32. The method of setting filter coefficients of the digital signal processing circuit according to claim 30 , comprising:
setting the filter coefficients of the second FIR filter to the inverse in phase of first impulse response of from the first DA, to the second AD converter; and
setting the filter coefficients of the first FIR filter to second impulse response of from the second DA converter, to the second AD converter.
33. The method of setting filter coefficients of the digital signal processing circuit according to claim 31 , wherein the first impulse response is impulse response of from the first DA converter, through an earphone microphone that converts the first analog signal of the first DA converter into voice and outputs and that converts inputted voice into the third analog signal and outputs, to the second AD converter.
34. The method of setting filter coefficients of the digital signal processing circuit according to claim 33 , wherein the first impulse response is one for a state where the earphone microphone is attached to an ear.
35. The method of setting filter coefficients of the digital signal processing circuit according to claim 30 , further comprising:
acquiring first impulse response of from the first DA converter, to the second AD converter;
acquiring second impulse response of from the second DA converter to the second AD converter;
setting the filter coefficients of the first FIR filter to the inverse in phase of the second impulse response; and
setting the filter coefficients of the second FIR filter to the first impulse response.
36. The method of setting filter coefficients of the digital signal processing circuit according to claim 30 , further comprising:
acquiring first impulse response of from the first DA converter, to the second AD converter;
acquiring second impulse response of from the second DA converter to the second AD converter;
setting the filter coefficients of the first FIR filter to the second impulse response; and
setting the filter coefficients of the second FIR filter to the inverse in phase of the first impulse response.
37. The method of setting filter coefficients of the digital signal processing circuit according to claim 35 , wherein the first impulse response is impulse response of from the first DA converter through an earphone microphone that converts the first analog signal of the first DA converter into voice and outputs and that converts inputted voice into the third analog signal and outputs, to the AD converter.
38. The method of setting filter coefficients of the digital signal processing circuit according to claim 37 , wherein the first impulse response is one for a state where the earphone microphone is attached to an ear.
39. A recording medium storing a program for setting filter coefficients of an echo prevention circuit, the echo prevention circuit comprising:
a processor;
a first AD converter configured to convert a voice signal into a first digital signal;
an input terminal to which the first digital signal is input;
a first FIR filter configured to process the first digital signal with a filter coefficient set therein and output a second digital signal;
a second FIR filter configured to process the first digital signal, that is input at the same time as into the first FIR filter, with a filter coefficient set therein and output a third digital signal;
a first DA converter configured to convert the second digital signal into a first analog signal;
a second DA converter configured to convert the third digital signal into a second analog signal;
an input/output terminal to which the first analog signal is output and a third analog signal is input;
a subtracter configured to subtract the second analog signal from a combined signal of the first analog signal and the third analog signal and output a fourth analog signal;
a second AD converter configured to convert the fourth analog signal into a fourth digital signal;
an output terminal to which the fourth digital signal is output; and
a third DA converter configured to convert the fourth digital signal from the output terminal into a fifth analog signal;
wherein the program causes the processor to implement a function to set the first FIR filter coefficients and the second FIR filter coefficients such that the fifth analog signal from the output terminal has only the first analog signal from the first DA converter removed or reduced.
40. A recording medium storing a program for setting filter coefficients of a digital signal processing circuit, the digital signal processing circuit comprising:
a processor;
a first input terminal to which a voice signal is input;
a first AD converter configured to convert the voice signal into a first digital signal;
a first FIR filter configured to process the first digital signal with a filter coefficient set therein and output a second digital signal;
a second FIR configured to process the first digital signal, that is input at the same time as into the first FIR filter, with a filter coefficient set therein and output a third digital signal;
a first DA converter configured to convert the second digital signal into a first analog signal;
a second DA converter configured to convert the third digital signal into a second analog signal;
a first output terminal to which the first analog signal is output;
a second output terminal to which the second analog signal is output;
a subtracter configured to subtract the second analog signal from a combined signal of the first analog signal and a third analog signal on an input/output signal common line and output a fourth analog signal;
a second input terminal to which the fourth signal is input;
a second AD converter configured to convert the fourth analog signal into a fourth digital signal;
a third DA converter configured to convert the fourth digital signal into a fifth analog signal; and
a third output terminal to which the fifth analog signal is output,
wherein the program causes the processor to implement a function to set the first FIR filter coefficients and the second FIR filter coefficients such that the fifth analog signal from the third output terminal has only the first analog signal from the first DA converter removed or reduced.