Differential amplifier

1. A differential amplifier comprising:

a first pair of complementary transistors with first control terminals coupled to a first input node of the differential amplifier and first driving terminals coupled to a first output node of the differential amplifier for driving a load;

a second pair of complementary transistors with second control terminals coupled to a second input node of the differential amplifier and second driving terminals coupled to a second output node of the differential amplifier for driving the load;

a current source configured to maintain a substantially constant total current flow through the first pair of complementary transistors and the second pair of complementary transistors; and

a reference voltage generator configured to generate a reference voltage based on a third pair of complementary transistors that is diode-connected for maintaining a common mode voltage level at the first output node and the second output node with reference to the reference voltage.

2. The differential amplifier of claim 1 , wherein the current source is a first current source, the differential amplifier further includes a second current source, and the first current source and the second current source are respectively configured to maintain a first substantially constant current from a high voltage source, and a second substantially constant current from a low voltage source.

3. The differential amplifier of claim 1 , further comprising:

a common mode feedback circuit configured to suppress a common mode response at the first output node and the second output node.

4. The differential amplifier of claim 3 , wherein the common mode feedback circuit is configured to maintain a common mode level at the first output node and the second output node with reference to the reference voltage.

5. The differential amplifier of claim 1 , wherein the third pair of complementary transistors has matching characteristics to the first pair and the second pair.

6. The differential amplifier of claim 1 , wherein the reference voltage generator is configured to generate a feedback signal to a voltage regulator to enable the voltage regulator to adjust a supply voltage to the differential amplifier based on the feedback signal.

7. The differential amplifier of claim 6 , wherein the feedback signal is provided to the voltage regulator that is on a same integrated circuit (IC) chip as the differential amplifier.

8. The differential amplifier of claim 6 , wherein the feedback signal is provided to the voltage regulator that is external to an integrated circuit (IC) chip that includes the differential amplifier.

9. The differential amplifier of claim 1 , further comprising:

adjustable resistive components configured to adjust a gain of the differential amplifier.

10. The differential amplifier of claim 1 , wherein the load includes a first current source load and a second current source load that are respectively coupled to the output nodes.

11. The differential amplifier of claim 10 , wherein the first current source load and the second current source load use transistors of a same type.

12. The differential amplifier of claim 10 , wherein the load includes a third current source load of a complementary type to the first current source load, and a fourth current source load of a complementary type to the second current source load.

13. The differential amplifier of claim 1 , wherein the first pair of complementary transistors includes a first P-type metal-oxide-semiconductor (MOS) transistor, and a first N-type MOS transistor, the first control terminals are gate terminals of the first P-type MOS transistor and the first N-type MOS transistor, and the first driving terminals are drain terminals of the first P-type MOS transistor and the first N-type MOS transistor; and the second pair of complementary transistors includes a second P-type MOS transistor, and a second N-type MOS transistor, the second control terminals are gate terminals of the second P-type MOS transistor and the second N-type MOS transistor, and the second driving terminals are drain terminals of the second P-type MOS transistor and the second N-type MOS transistor.

14. A circuit, comprising:

a pair of complementary transistors configured to have matching characteristics as complementary transistors pairs in a differential amplifier and to have diode-connected topology; and

a feedback signal generating circuit configured to generate a feedback signal based on a voltage drop on the pair of complementary transistors, the feedback signal being used to adjust a supply voltage to the differential amplifier.

15. The circuit of claim 14 , further comprising:

a voltage regulator configured to regulate the supply voltage to the differential amplifier based on the feedback signal.

16. The circuit of claim 14 , wherein the feedback signal is provided to an external voltage regulator that provides the supply voltage to the differential amplifier.

17. A method, comprising:

receiving a pair of differential input signals at a first input node and a second input node of a differential amplifier, the first input node controlling control terminals of a first pair of N-type and P-type transistors, and the second input node controlling control terminals of a second pair of N-type and P-type transistors;

maintaining a substantially constant total current flowing through the transistors of a same type;

driving a load coupled between a first output node and a second output node of the differential amplifier with a current controlled by both types of transistors;

generating a reference voltage based on a third pair of complementary transistors that is diode-connected; and

maintaining a common mode voltage level at the first output node and the second output node with reference to the reference voltage.

18. The method of claim 17 , further comprising:

suppressing a common mode response of the first output node and the second output node.