IP Library › Granted Patent US 8,940,620
Granted Patent B2
US 8,940,620 · App. 13/374,206 · Granted Jan 27, 2015

Composite wafer for fabrication of semiconductor devices

Inventors: Alexei Koudymov (Troy, NY); Jamal Ramdani (Raritan, NJ); Kierthi Swaminathan (Highland Park, NJ)
Assignee: Power Integrations, Inc.
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Quick Facts
Patent No.
US 8,940,620
App. No.
13/374,206
Granted
Jan 27, 2015
Kind
B2
Abstract

A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate.

Claims (22)

1. A method comprising:

(a) forming an interlayer that bonds a top surface of a carrier substrate to a bottom surface of a first substrate, the first substrate being of a first semiconductor material type and also having a top surface and a first thickness, the carrier substrate being of a second semiconductor material type and having a second thickness greater than the first thickness, the interlayer comprising silicon dioxide;

(b) forming one or more nitride layers over the top surface of the first substrate;

(c) fabricating nitride-based semiconductor devices in the one or more nitride layers; and

(d) de-bonding the top surface of the carrier substrate from the bottom surface of the first substrate.

2. The method of claim 1 wherein in the first substrate comprises sapphire.

3. The method of claim 1 wherein the second thickness is approximately 400 μm thick or greater.

4. The method of claim 1 wherein the carrier substrate is selected from the group consisting of sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, boron nitride, and zinc oxide.

5. The method of claim 1 wherein the de-bonding step comprises performing a wet etch in a chemical solution.

6. The method of claim 1 wherein the nitride-based semiconductor devices are formed on individual dies of a wafer, and further comprising separating the individual dies prior to the de-bonding step.

7. The method of claim 1 wherein the nitride-based semiconductor devices are formed on individual dies of a wafer, and further comprising separating the individual dies after the de-bonding step.

8. The method of claim 1 further comprising polishing the top surface of the first substrate prior to forming the one or more nitride layers.

9. The method of claim 8 wherein the polishing of the top surface results in an atomically-flat top surface.

10. The method of claim 1 wherein the first and second semiconductor material types have respective first and second coefficients of thermal expansion that are substantially matched to one another.

11. The method of claim 1 wherein the first semiconductor material type is selected from a group consisting of sapphire, diamond, gallium nitride, aluminum nitride, boron nitride, silicon carbide, and zinc oxide.

12. The method of claim 1 wherein the second semiconductor material type is selected from a group consisting of silicon and sapphire.

13. The method of claim 1 wherein the nitride-based semiconductor devices are fabricated as a plurality of die, and further comprising:

de-bonding the first substrate from the carrier substrate; and

individuating each of the die.

14. The method of claim 1 wherein the nitride-based semiconductor devices are fabricated as a plurality of die, and wherein the de-bonding comprises:

individuating each of the die; and

for each of the individuated die, de-bonding the first substrate from the carrier substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2012
From: KOUDYMOV, ALEXEI; RAMDANI, JAMAL; SWAMINATHAN, KIERTHI
To: POWER INTEGRATIONS, INC.
Reel/Frame 027842/0265 →
Continuity (1)
Related Publication 20130157440A1 · Jun 20, 2013