Capacitorless memory device
According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.
1. A capacitorless memory device comprising: at least one capacitorless memory cell, each capacitorless memory cell including,
a bit line on a substrate;
a read transistor including,
a first impurity layer, a second impurity layer, and a third impurity layer stacked in a vertical direction on the bit line,
the first and third impurity layers being a first conductive type, and
the second impurity layer being a second conductive type that is different from the first conductive type;
a write transistor including,
a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate,
the source layer being adjacent to a side surface of the second impurity layer of the read transistor, and
a gate line adjacent to a side surface of the body layer, the gate line being spaced apart from the side surface of the body layer; and
a ground line that is electrically connected to the third impurity layer.
2. The capacitorless memory device of claim 1 , wherein the write transistor further includes:
a source barrier layer between the source layer and the body layer, and
a drain barrier layer between the drain layer and the body layer.
3. The capacitorless memory device of claim 1 , wherein the body layer includes:
a first body layer,
a second body layer over the first body layer, and
a shutter layer between the first and second body layers.
4. The capacitorless memory device of claim 1 , wherein
the source layer and the drain layer include metal, and
the source layer and the body layer form a first Schottky contact, and
the drain layer and the body layer form a second Schottky contact.
5. The capacitorless memory device of claim 1 , wherein
an upper surface of the gate line is as high as or higher than an upper surface of the body layer, and
a lower surface of the gate line is as high as or lower than a lower surface of the body layer.
6. The capacitorless memory device of claim 5 , wherein the lower surface of the gate line and a lower surface of the source layer are at equal heights.
7. The capacitorless memory device of claim 1 , wherein a lower surface of the source layer is as low as or lower than a lower surface of the second impurity layer.
8. The capacitorless memory device of claim 7 , wherein an upper surface of the source layer is higher than upper surfaces of the second impurity layer and the third impurity layer.
9. The capacitorless memory device of claim 1 , wherein the gate line surrounds the side surface of the body layer.
10. The capacitorless memory device of claim 9 , wherein the gate line surrounds the side surface of the drain layer.
11. The capacitorless memory device of claim 1 , further comprising:
a fourth impurity layer electrically connected to the ground line, wherein
the fourth impurity layer is the second conductive type, and
the fourth impurity layer is adjacent to the second impurity layer.
12. The capacitorless memory device of claim 1 ,
wherein
the bit line extends in a first direction,
the gate line and the ground line extend in a second direction, and
the second direction is different than the first direction.
13. The capacitorless memory device of claim 1 , wherein the first impurity layer is between the gate line and the bit line in the vertical direction.
14. A capacitorless memory device comprising:
a bit line on a substrate;
first and second capacitorless memory cells, the first and second capacitorless memory cells each including,
a read transistor including,
a first impurity layer, a second impurity layer, and a third impurity layer stacked in a vertical direction on the bit line,
the first and third impurity layers being a first conductive type,
the second impurity layer being a second conductive type that is different from the first conductive type, and
a write transistor including,
a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate,
the source layer being adjacent to a side surface of the second impurity layer of the read transistor, and
a gate line that is adjacent to a side surface of the body layer and spaced apart from the side surface of the body layer,
wherein the first impurity layer is between the gate line and the bit line in the vertical direction.
15. The capacitorless memory device of claim 14 , wherein the second impurity layer of the first capacitorless memory cell and the second impurity layer of the second capacitorless memory cell are integrally formed.
16. A capacitorless memory device comprising:
a bit line;
a ground line;
a data word line; and
at least one capacitorless memory cell including,
a read transistor on the bit line, the read transistor including,
a source structure electrically connected to the bit line,
a drain structure electrically connected to the ground line,
a body structure between the source and drain structures, and
a write transistor including,
a vertical stack including a source layer, a body layer, and a drain layer,
the drain layer being connected to the data word line, and
the source layer being configured to function as a gate electrode for the read transistor, and
a gate adjacent to the vertical stack.
17. The capacitorless memory device of claim 16 , further comprising:
a first interwall insulation layer between the source layer of the write transistor and at least one of the source structure, body structure, and drain structure of the read transistor; and
a substrate, wherein
the source structure, body structure, and drain structure of the read transistor are sequentially stacked on the substrate, and
the ground line is electrically connected to the body structure of the read transistor.
18. The capacitorless memory device of claim 17 , wherein
the body layer and the drain layer of the write transistor are surrounded by the gate of the write transistor,
the source structure and the drain structure of the read transistor are a first conductive type,
the body structure is a second conductive type, and
the second conductive type is different than the first conductive type.
19. The capacitorless memory device of claim 16 ,
a first interwall insulation layer between the source layer of the write transistor and at least one of the source structure, body structure, and drain structure of the read transistor; and
a substrate, wherein
the source structure, body structure, and drain structure of the read transistor are sequentially stacked on the substrate,
the ground line is not directly connected to the body structure of the read transistor.
20. The capacitorless memory device of claim 16 , further comprising:
a device isolation layer between the ground line and the bit line, wherein
the read transistor is a vertical-type transistor structure,
the source structure and the drain structure of the read transistor are a first conductive type,
the body structure is a second conductive type, and
the second conductive type is different than the first conductive type.