Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
1. A semiconductor device, comprising:
a semiconductor body disposed above a substrate;
a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and
sidewall spacers disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
2. The semiconductor device of claim 1 , wherein a portion of the source and drain regions not under the sidewall spacers has a height and a width greater than the height and the width of the portion of the source and drain regions under the sidewall spacers.
3. The semiconductor device of claim 1 , wherein a portion of the source and drain regions not under the sidewall spacers has a height and a width approximately the same as the height and the width of the portion of the source and drain regions under the sidewall spacers.
4. The semiconductor device of claim 1 , wherein at least a portion of the source and drain regions is an epitaxial portion of the source and drain regions.
5. The semiconductor device of claim 4 , wherein the epitaxial portion of the source and drain regions comprise a semiconductor material different than the channel region.
6. The semiconductor device of claim 1 , wherein the substrate is a crystalline substrate, and the semiconductor body is continuous with the crystalline substrate.
7. The semiconductor device of claim 1 , wherein a dielectric layer is disposed between the semiconductor body and the substrate, and the semiconductor body is discontinuous with the substrate.
8. The semiconductor device of claim 1 , wherein the channel region has a height approximately in the range of 30-50 nanometers and a width approximately in the range of 10-30 nanometers, the height of the channel region is approximately 1-2 nanometers less than the height of the portion of the source and drain regions under the sidewall spacers, and the width of the channel region is approximately 2-4 nanometers less than the width of the portion of the source and drain regions under the sidewall spacers.
9. The semiconductor device of claim 1 , wherein the height of the portion of the source and drain regions under the sidewall spacers is approximately 1-7% greater than the height of the channel region, and the width of the portion of the source and drain regions under the sidewall spacers is approximately 6-40% greater than the width of the channel region.
10. The semiconductor device of claim 1 , wherein the channel region is coupled to the portion of the source and drain regions under the sidewall spacers by a step feature.
11. The semiconductor device of claim 1 , wherein the channel region is coupled to the portion of the source and drain regions under the sidewall spacers by a graded feature.
12. The semiconductor device of claim 11 , wherein the graded feature comprises a facet.
13. The semiconductor device of claim 11 , wherein the graded feature comprises a rounded corner.
14. The semiconductor device of claim 11 , wherein the graded feature reduces overlap capacitance and spreading resistance during operating of the semiconductor device.
15. The semiconductor device of claim 1 , wherein the semiconductor device is disposed above the same substrate as a second semiconductor device having a channel region, and wherein the narrowest width of the channel region of the second semiconductor device is greater than the narrowest width of the channel region of the semiconductor device.