IP Library › Granted Patent US 8,941,246
Granted Patent B2
US 8,941,246 · App. 13/623,249 · Granted Jan 27, 2015

Semiconductor device and manufacturing method thereof

Inventors: Masayuki Miura (Ota-ku, JP); Taku Kamoto (Yokohama, JP); Takao Sato (Edogawa-ku, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L24/94H01L27/115H01L24/97H01L25/0657H01L2224/13025H01L2224/14181H01L2224/16145H01L2224/16225H01L2224/32145H01L2224/32225H01L2224/48227H01L2224/73204H01L2224/73207H01L2224/73253H01L2224/73265H01L2224/97H01L2924/15311H01L2224/45144H01L21/568H01L2224/94H01L2225/0651H01L2225/06517H01L2225/06589H01L2225/06513H01L2225/06541
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,941,246
App. No.
13/623,249
Granted
Jan 27, 2015
Kind
B2
Abstract

In one embodiment, a semiconductor device includes a chip stacked body disposed on an interposer substrate and an interface chip mounted on the chip stacked body. The chip stacked body has plural semiconductor chips, and is electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and bump electrodes. The interface chip is electrically connected to the interposer substrate via a rewiring layer formed on a surface of an uppermost semiconductor chip in the stacking order or through electrodes provided in the interface chip.

Claims (22)

1. A semiconductor device, comprising:

an interposer substrate having a first surface provided with an external connection terminal and a second surface provided with an internal connection terminal;

a chip stacked body, disposed on the second surface of the interposer substrate, having plural semiconductor chips sequentially stacked, the plural semiconductor chips being electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and a first bump electrode connecting between the through electrodes, the lowermost semiconductor chip being electrically connected to the interposer substrate via at least one semiconductor chip having the through electrode, and an uppermost semiconductor chip in the stacking order having a rewiring layer provided on a surface thereof; and

an interface chip mounted on the uppermost semiconductor chip, electrically connected to the uppermost semiconductor chip via a second bump electrode, and electrically connected to the internal connection terminal via the rewiring layer.

2. The semiconductor device according to claim 1 ,

wherein the chip stacked body is disposed so that the lowermost semiconductor chip is positioned on the second surface side of the interposer substrate, and

wherein the interface chip is electrically connected to the internal connection terminal via a bonding wire connected to the rewiring layer.

3. The semiconductor device according to claim 2 ,

wherein the lowermost semiconductor chip is adhered to the second surface of the interposer substrate.

4. The semiconductor device according to claim 2 ,

wherein the chip stacked body is disposed on a chip mounting portion of a supporting substrate and the supporting substrate is adhered to the second surface of the interposer substrate, and

wherein the supporting substrate has a groove provided in a periphery of the chip mounting portion, a resin is filled into a gap between the semiconductor chips, and a portion of the resin protruded from the gap is held in the groove.

5. The semiconductor device according to claim 1 ,

wherein the chip stacked body is disposed so that the uppermost semiconductor chip is positioned on the second surface side of the interposer substrate, and

wherein the interface chip is electrically connected to the internal connection terminal via a third bump electrode which is connected to the rewiring layer and has a size larger than that of the second bump electrode.

6. The semiconductor device according to claim 5 ,

wherein the chip stacked body is disposed on a chip mounting portion of a supporting substrate and the supporting substrate is adhered to the second surface of the interposer substrate, and

wherein the supporting substrate has a groove provided in a periphery of the chip mounting portion, a resin is filled into a gap between the semiconductor chips, and a portion of the resin protruded from the gap is held in the groove.

7. The semiconductor device according to claim 1 ,

wherein the lowermost semiconductor chip has a thickness thicker than that of the other semiconductor chips.

8. The semiconductor device according to claim 1 ,

wherein the chip stacked body has a spacer disposed in a gap between the semiconductor chips.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2012
From: MIURA, MASAYUKI; KAMOTO, TAKU; SATO, TAKAO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 029463/0343 →
Priority Claims (2)
JP 2011-206869 · Sep 22, 2011 · national
JP 2012-200287 · Sep 12, 2012 · national
Continuity (1)
Related Publication 20130075895A1 · Mar 28, 2013