Protocol for memory power-mode control
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
1. A memory device having a memory core, the memory device comprising:
input receivers including a first set of receivers and a second set of receivers, the first set of receivers configured to receive commands and the second set of receivers configured to receive data; and
a register to store a value that indicates whether the second set of receivers are powered down in response to a control signal.
2. The memory device of claim 1 , wherein, at a time in which the second set of receivers are powered down, the first set of receivers receive a command.
3. The memory device of claim 1 , wherein each input receiver of the input receivers comprises a current source; and
wherein when a respective receiver is powered down, the current source corresponding to the respective receiver is powered down.
4. The memory device of claim 1 , further including transmitters to output data, wherein the register stores information that indicates whether the transmitters are powered down in response to the control signal.
5. The memory device of claim 1 ,
wherein while the memory core is in one of a self-refresh state, an idle standby state, and an active standby state, the control signal and a calibration command facilitate calibration of the receivers.
6. The memory device of claim 1 , wherein a command received prior to the second set of receivers being powered down indicates an operational state for the second set of receivers after the second set of receivers are powered up.
7. The memory device of claim 6 , wherein the command indicates a clock frequency for the second set of receivers after the second set of receivers are powered up.
8. The memory device of claim 1 , further comprising an interface which remains operational while the second set of receivers are powered down, and wherein the interface facilitates reading from registers in the memory device when the second set of receivers are powered down.
9. A method of operating a memory device having a memory core, the method comprising:
receiving commands and data via a number of input receivers, the input receivers including a first set of receivers that receive the commands and a second set of receivers that receive the data; and
storing a value in a register, the value indicating whether the second set of receivers are powered down in response to a control signal.
10. The method of claim 9 , wherein at a time in which the second set of receivers are powered down, the method further comprises receiving a command via the first set of receivers.
11. The method of claim 9 , wherein each input receiver of the input receivers comprises a current source; and
wherein when a respective receiver is powered down, the method further comprises powering down the current source corresponding to the respective receiver.
12. The method of claim 9 , wherein the memory device includes transmitters to output data; and
wherein the method comprises storing in the register information that indicates whether the transmitters are powered down in response to the control signal.
13. The method of claim 12 , wherein when a respective transmitter of the transmitters is powered down, the method further comprises powering down a current source associated with the respective transmitter.