IP Library Granted Patent US 8,946,789
Granted Patent B2
US 8,946,789 · App. 13/295,620 · Granted Feb 3, 2015

Semiconductor device, method of manufacturing the same, and electronic device including the semiconductor device

Inventors: Sun-kook Kim (Hwaseong-si, KR); Woong Choi (Seongman-si, KR); Sang-yoon Lee (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L29/0673H01L29/1029B82Y10/00B82Y40/00H01L29/1033H01L29/775H01L29/78648H01L29/78696H01L51/0048H01L51/0558H01L51/0579H01L51/0554H01L51/0562H01L51/424Y02E10/549
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Quick Facts
Patent No.
US 8,946,789
App. No.
13/295,620
Granted
Feb 3, 2015
Kind
B2
Abstract

An example embodiment relates to a transistor including a channel layer. A channel layer of the transistor may include a plurality of unit layers spaced apart from each other in a vertical direction. Each of the unit layers may include a plurality of unit channels spaced apart from each other in a horizontal direction. The unit channels in each unit layer may form a stripe pattern. Each of the unit channels may include a plurality of nanostructures. Each nanostructure may have a nanotube or nanowire structure, for example a carbon nanotube (CNT).

Claims (23)

1. A transistor comprising:

a channel layer,

the channel layer including a plurality of unit layers spaced apart from each other in a vertical direction, and

each of the plurality of unit layers including a plurality of unit channels spaced apart from each other in a horizontal direction, each of the plurality of unit channels including a plurality of nanostructures, the plurality of nanostructures in each of the plurality of unit channels including a network structure, the plurality of unit channels in each of the plurality of unit layers forming a stripe pattern;

a source arranged laterally on one side of the channel layer;

a drain arranged laterally on an other side of the channel layer; and

a gate corresponding to the channel layer; and

an insulation layer between every two adjacent unit layers, the insulation layer including a first insulation single layer between first and second unit layers of the plurality of unit layers, the first and second unit layers directly contacting lower and upper surfaces of the first insulation single layer, respectively.

2. The transistor of claim 1 ,

each of the plurality of nanostructures include one of a nanotube and a nanowire.

3. The transistor of claim 2 , wherein

the plurality of nanostructures include carbon nanotubes (CNTs).

4. The transistor of claim 1 , wherein

a ratio (L/W) of a length (L) to a width (W) of each of the plurality of unit channels is equal to or more than about 5.

5. The transistor of claim 1 , wherein

the gate is a first gate,

the transistor further includes a second gate spaced apart from the first gate, and

the channel layer is disposed between the first and second gates.

6. An electronic device comprising the transistor of claim 1 .

7. The electronic device of claim 6 , wherein

the electronic device is a display.

8. The transistor of claim 1 , wherein

the first and second unit layers have a same width as the first insulation single layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2011
From: KIM, SUN-KOOK; CHOI, WOONG; LEE, SANG-YOON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 027255/0730 →
Priority Claims (1)
KR 10-2011-0019650 · Mar 4, 2011 · national
Continuity (1)
Related Publication 20120223288A1 · Sep 6, 2012