Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.
1. A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, comprising:
a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer;
a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to at least some of the plurality of metal segments in the bottom most layer; and
a passivation layer having one or more openings that correspond spatially with the one or more openings at the dielectric layer, wherein the passivation layer is formed on the dielectric layer.
2. The substrate-less interposer of claim 1 , wherein the plurality of metal segments comprise copper.
3. The substrate-less interposer of claim 1 , further comprising an underbump metal (UBM) layer in contact with the at least some of the plurality of metal segments in the bottom most layer, the UBM layer formed on the bottom most layer.
4. The substrate-less interposer of claim 1 , wherein the substrate-less interposer is configured to support a plurality of IC dies on a top surface of a top most layer of the metallization layers.
5. The substrates-less interposer of claim 4 , wherein the plurality of IC dies comprises heterogeneous IC dies.
6. The substrate-less interposer of claim 4 , wherein the plurality of IC dies comprises homogeneous IC dies.
7. The substrate-less interposer of claim 4 , wherein different groups of the plurality of metal segments in the bottom most layer of the metallization layers correspond respectively to a plurality of IC dies.
8. The substrate-less interposer of claim 7 , wherein the different groups of the plurality of metal segments have different respective segment densities.
9. The substrate-less interposer of claim 1 , wherein each of the plurality of the metallization layers comprises a plurality of metal segments, and a number of the metal segments in one of the metallization layers is different from a number of the metal segments in another one of the metallization layers.
10. A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, comprising:
a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer;
a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to at least some of the plurality of metal segments in the bottom most layer;
wherein the substrate-less interposer is configured to support a plurality of IC dies on a top surface of a top most layer of the metallization layers; and
wherein different groups of the plurality of metal segments in the bottom most layer of the metallization layers correspond respectively to a plurality of IC dies.
11. The substrate-less interposer of claim 10 , wherein the plurality of metal segments comprise copper.
12. The substrate-less interposer of claim 10 , further comprising an underbump metal (UBM) layer in contact with the at least some of the plurality of metal segments in the bottom most layer, the UBM layer formed on the bottom most layer.
13. The substrates-less interposer of claim 10 , wherein the plurality of IC dies comprises heterogeneous IC dies.
14. The substrate-less interposer of claim 10 , wherein the plurality of IC dies comprises homogeneous IC dies.
15. The substrate-less interposer of claim 10 , wherein the different groups of the plurality of metal segments have different respective segment densities.
16. The substrate-less interposer of claim 10 , wherein each of the plurality of the metallization layers comprises a plurality of metal segments, and a number of the metal segments in one of the metallization layers is different from a number of the metal segments in another one of the metallization layers.
17. A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, comprising:
a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer;
a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to at least some of the plurality of metal segments in the bottom most layer;
wherein each of the plurality of the metallization layers comprises a plurality of metal segments; and
wherein a number of the metal segments in one of the metallization layers is different from a number of the metal segments in another one of the metallization layers.
18. The substrate-less interposer of claim 17 , wherein the plurality of metal segments comprise copper.
19. The substrate-less interposer of claim 17 , further comprising an underbump metal (UBM) layer in contact with the at least some of the plurality of metal segments in the bottom most layer, the UBM layer formed on the bottom most layer.
20. The substrate-less interposer of claim 17 , wherein the substrate-less interposer is configured to support a plurality of IC dies on a top surface of a top most layer of the metallization layers.
21. The substrates-less interposer of claim 20 , wherein the plurality of IC dies comprises heterogeneous IC dies.
22. The substrate-less interposer of claim 20 , wherein the plurality of IC dies comprises homogeneous IC dies.
23. A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, comprising:
a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and
a dielectric silicon dioxide layer formed on the bottom surface of the bottom most layer, wherein the dielectric silicon dioxide layer includes one or more openings for providing contact to at least some of the plurality of metal segments in the bottom most layer.