Charge-discharge control circuit, semiconductor integrated circuit, method of controlling charging and discharging
A charge-discharge control circuit includes a cell balance detection circuit that detects that a voltage of a cell reaches a predetermined voltage; a memory circuit that stores the cell that reaches the predetermined voltage first among plural of the cells; bypass circuits respectively connected to the plural cells in parallel, each of the bypass circuits including a switch unit for bypassing the current that flows through the corresponding cell when charging; and a control circuit that controls the switch units, wherein the control circuit controls the switch unit based on the cell stored in the memory circuit so that an ON/OFF status of the switch unit is maintained from a start to an end of a next charging operation subsequent to a charging operation during which the cell is stored in the memory circuit.
1. A charge-discharge control circuit for controlling cycles of charging and discharging of a secondary battery including plural cells, comprising:
a cell balance detection circuit that detects that a voltage of at least one of the plural cells reaches a predetermined voltage in a first charging operation;
a memory circuit that memorizes a first cell that reaches the predetermined voltage first among the plural cells in the first charging operation;
bypass circuits respectively connected to the plural cells in parallel, each of the bypass circuits including a switch unit for bypassing the current that flows through the corresponding cell when charging; and
a control circuit that controls,
in a second charging operation after the secondary battery charged by the first charging operation is discharged, the switch unit corresponding to the first cell memorized by the memory circuit so that the switch unit corresponding to the first cell is switched on from a start to an end of the second charging operation.
2. The charge-discharge control circuit according to claim 1 ,
wherein the predetermined voltage is a charge terminate voltage that detects termination of the cells.
3. The charge-discharge control circuit according to claim 1 , further comprising:
an over-discharge detection circuit that detects that a voltage of the cell becomes lower than or equal to a predetermined voltage;
a discharge control circuit that controls discharging of the cells based on the detected result by the over-discharge detection circuit;
a charge termination detection circuit that detects that a voltage of the cell becomes higher or equal to a charge terminate voltage; and
a charge control circuit that controls charging of the cells based on the charge termination detection circuit or the cell balance detection circuit.
4. The charge-discharge control circuit according to claim 3 , further comprising:
a transistor for controlling discharging for which ON/OFF is controlled based on the detected result by the over-discharge detection circuit; and
a transistor for controlling charging for which ON/OFF is controlled by the charge control circuit.
5. A semiconductor integrated circuit for controlling cycles of charging and discharging of a secondary battery including plural cells, comprising:
a cell balance detection circuit that detects that a voltage of at least one of the plural cells reaches a predetermined voltage in a first charging operation;
a memory circuit that memorizes a first cell that reaches the predetermined voltage first among the plural cells in the first charging operation; and
a control circuit that controls switch units of bypass circuits, each of the bypass circuits including the switch unit for bypassing the current that flows through the corresponding cell when charging;
wherein the control circuit controls, in a second charging operation after the secondary battery charged by the first charging operation is discharged, the switch unit corresponding to the first cell memorized by the memory circuit so that the switch unit corresponding to the first cell is switched on from a start to an end of the second charging operation.
6. The semiconductor integrated circuit according to claim 5 , further comprising:
the bypass circuits.
7. A method of controlling charging and discharging by a charge-discharge control circuit that controls cycles of charging and discharging of a secondary battery including plural cells, comprising:
a cell balance detecting step of detecting that a voltage of at least one of the plural cells reaches a predetermined voltage in a first charging operation;
a memorizing step of memorizing a first cell in a memory circuit that reaches the predetermined voltage first among the plural cells in the first charging operation; and
a controlling step of controlling switch units of bypass circuits, each of the bypass circuits including the switch unit for bypassing the current that flows through the corresponding cell when charging;
wherein in the controlling step, in a second charging operation after the secondary battery charged by the first charging operation is discharged, the switch unit corresponding to the first cell memorized in the memorizing is controlled so that the switch unit corresponding to the first cell is switched on from a start to an end of the second charging operation.
8. The charge-discharge control circuit according to claim 1 ,
wherein each of the bypass circuits functions to decrease the current that flows through the corresponding cell when charging.
9. The charge-discharge control circuit according to claim 1 ,
wherein the cell balance detection circuit that detects that a voltage of at least one of the plural cells reaches a predetermined voltage in the second charging operation,
wherein the memory circuit memorizes a second cell that reaches the predetermined voltage first among the plural cells in the second charging operation, and
wherein the control circuit controls, in a third charging operation after the secondary battery charged by the second charging operation is discharged, the switch unit corresponding to the second cell memorized by the memory circuit so that the switch unit corresponding to the second cell is switched on from a start to an end of the third charging operation.
10. The semiconductor integrated circuit according to claim 5 ,
wherein each of the bypass circuits functions to decrease the current that flows through the corresponding cell when charging.
11. The semiconductor integrated circuit according to claim 5 ,
wherein the cell balance detection circuit that detects that a voltage of at least one of the plural cells reaches a predetermined voltage in the second charging operation,
wherein the memory circuit memorizes a second cell that reaches the predetermined voltage first among the plural cells in the second charging operation, and
wherein the control circuit controls, in a third charging operation after the secondary battery charged by the second charging operation is discharged, the switch unit corresponding to the second cell memorized by the memory circuit so that the switch unit corresponding to the second cell is switched on from a start to an end of the third charging operation.
12. The method of controlling charging and discharging according to claim 7 ,
wherein each of the bypass circuits functions to decrease the current that flows through the corresponding cell when charging.
13. The method of controlling charging and discharging according to claim 7 , further comprising:
a second cell balance detecting step of detecting that a voltage of at least one of the plural cells reaches a predetermined voltage in the second charging operation;
a second memorizing step of memorizing a second cell in the memory circuit that reaches the predetermined voltage first among the plural cells in the second charging operation; and
a second controlling step of controlling, in a third charging operation after the secondary battery charged by the second charging operation is discharged, the switch unit corresponding to the second cell memorized in the memorizing is controlled so that the switch unit corresponding to the second cell is switched on from a start to an end of the third charging operation.