IP Library Granted Patent US 8,949,696
Granted Patent B2
US 8,949,696 · App. 13/770,030 · Granted Feb 3, 2015

Systems and methods for trapping set disruption

Inventors: Chung-Li Wang (San Jose, CA); Fan Zhang (Milpitas, CA); Qi Qi (San Jose, CA); Shu Li (San Jose, CA); Shaohua Yang (San Jose, CA)
Assignee: LSI Corporation
G11B20/1833H03M13/1111H03M13/1117H03M13/1122H03M13/1128H03M13/1142H03M13/6331H03M13/6343H03M13/658H03M13/2957
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Quick Facts
Patent No.
US 8,949,696
App. No.
13/770,030
Granted
Feb 3, 2015
Kind
B2
Abstract

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including utilization of different scaling values on a portion by portion basis during the data decoding.

Claims (57)

1. A data processing system, the data processing system comprising:

a data decoder circuit operable to apply a data decode algorithm to a decoder input to yield a decoded output, wherein the decoder input includes at least a first portion and a second portion; and

wherein applying the data decoding algorithm to the decoder input includes:

determining a first condition associated with the first portion;

determining a second condition associated with the second portion;

applying a first scaling value to the first portion based at least in part upon the first condition, and

applying a second scaling value to the second portion based at least in part upon the second condition.

2. The data processing system of claim 1 , wherein determining the first condition and determining the second condition comprises:

calculating a syndrome of the first portion to yield a first syndrome value, and wherein the first condition is a zero value of the first syndrome; and

calculating a syndrome of the second portion to yield a second syndrome value, and wherein the second condition is a non-zero value of the second syndrome.

3. The data processing system of claim 1 , wherein the first portion is a first row of the decoder input, and wherein the second portion is a second row of the decoder input.

4. The data processing system of claim 1 , wherein applying the data decoding algorithm to the decoder input further includes:

determining a third condition associated with the decoder input; and

applying a third scaling value to both the first portion and the second portion based at least in part upon the third condition.

5. The data processing system of claim 4 , wherein the third condition is the absence of a trapping set associated with the decoder input.

6. The data processing system of claim 1 , wherein applying the data decoding algorithm to the decoder input further includes:

determining a third condition associated with the decoder input;

wherein applying the first scaling value to the first portion is based at least in part upon a combination of the first condition and the third condition; and

wherein applying the second scaling value to the second portion is based at least in part upon a combination of the second condition and the third condition.

7. The data processing system of claim 6 , wherein the third condition is the occurrence of a trapping set associated with the decoder input.

8. The data processing system of claim 1 , wherein the data processing system further comprises:

a data detector circuit operable to apply a data detection algorithm to a data input to yield a detected output, wherein the decoder input is derived from the detected output.

9. The data processing system of claim 8 , wherein the data detector circuit is selected from a group consisting of: a Viterbi algorithm data detector circuit, and a maximum a posteriori data detector circuit.

10. The data processing system of claim 1 , wherein the data decoder circuit is selected from a group consisting of: a layered low density parity check data decoder circuit, and a non-layered low density parity check data decoder circuit.

11. The data processing system of claim 1 , wherein the data processing system is implemented as an integrated circuit.

12. The data processing system of claim 1 , wherein the data processing system is incorporated in a device selected from a group consisting of: a storage device, and a data transmission device.

13. A data processing method, the data processing method comprising:

receiving a decoder input, wherein the decoder input includes a first portion and a second portion;

applying a data decoding algorithm to the decoder input by a data decoder circuit, wherein applying the data decoding algorithm includes:

determining a first condition associated with the first portion;

determining a second condition associated with the second portion;

applying a first scaling value to the first portion based at least in part upon the first condition, and

applying a second scaling value to the second portion based at least in part upon the second condition.

14. The method of claim 13 , wherein determining the first condition comprises:

calculating a syndrome of the first portion to yield a first syndrome value, and wherein the first condition is a zero value of the first syndrome; and

calculating a syndrome of the second portion to yield a second syndrome value, and wherein the second condition is a non-zero value of the second syndrome.

15. The method of claim 13 , wherein the first portion is a first row of the decoder input, and wherein the second portion is a second row of the decoder input.

16. The method of claim 13 , wherein applying the data decoding algorithm to the decoder input further includes:

determining a third condition associated with the decoder input, wherein the third condition is the absence of a trapping set associated with the decoder input; and

applying a third scaling value to both the first portion and the second portion based at least in part upon the third condition.

17. The method of claim 13 , wherein applying the data decoding algorithm to the decoder input further includes:

determining a third condition associated with the decoder input, wherein the third condition is the occurrence of a trapping set associated with the decoder input;

wherein applying the first scaling value to the first portion is based at least in part upon a combination of the first condition and the third condition; and

wherein applying the second scaling value to the second portion is based at least in part upon a combination of the second condition and the third condition.

18. The method of claim 13 , wherein the method further comprises:

receiving a codeword;

applying a data detection algorithm to a codeword to yield a detected output, wherein the decoder input is derived from the detected output.

19. A data processing system, the data processing system comprising:

a data decoder circuit operable to apply a data decode algorithm to a decoder input to yield a decoded output, wherein the decoder input includes at least a first row and a second row; and

wherein applying the data decoding algorithm to the decoder input includes:

determining a first condition associated with the first row of the decoder input;

determining a second condition associated with the second row of the decoder input;

applying a first scaling value to the first row based at least in part upon the first condition, and

applying a second scaling value to the second row based at least in part upon the second condition.

20. The data processing system of claim 19 , wherein applying the data decoding algorithm to the decoder input further includes:

determining an absence of a trapping set associated with the decoder input; and

applying a third scaling value to both the first row and the second row based at least in part upon the absence of a trapping set.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2013
From: WANG, CHUNG-LI; ZHANG, FAN; QI, QI; LI, SHU; YANG, SHAOHUA
To: LSI CORPORATION
Reel/Frame 029862/0372 →
Continuity (1)
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