Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics

1. A method of configuring an asynchronous reconfigurable logic fabric for use in an integrated circuit, the method comprising:

providing an electronic design tool;

configuring the electronic design tool to operate in accordance with asynchronous dataflow representations, the asynchronous dataflow representations being selected from a group comprising at least one of merge, copy, function, split, sink, source, or initiate; and

using the electronic design tool to configure an embedded array comprising asynchronous logic elements that include one or more of the asynchronous dataflow representations, said asynchronous logic elements being programmable to carry out logic operations on signals provided at asynchronous logic element inputs and to asynchronously provide operation results at asynchronous logic element outputs, and said asynchronous logic elements include at least one multiplier unit coupled to at least one memory unit.

2. The method of claim 1 , wherein said at least one multiplier unit and said at least on memory unit are directly coupled.

3. The method of claim 1 , wherein said at least one multiplier unit and said at least one memory unit are coupled by an interconnecting grid.

4. The method of claim 1 , wherein said at least one multiplier unit and said at least one memory unit are coupled by a first connection and a second connection comprising respectively a direct connection and an interconnecting grid.

5. The method of claim 4 , wherein said asynchronous reconfigurable logic fabric further comprises at least one programmable connection unit for selecting between said direct connection and said interconnecting grid.

6. The method of claim 1 , wherein said at least one multiplier unit and said at least one memory unit are programmable.

7. The method of claim 1 , further comprising:

using the electronic design tool to configure a programmable input/output block that couples said asynchronous logic element inputs and said asynchronous logic element outputs to external circuits, said programmable input/output block being programmable for synchronous operation with said external circuits.

8. The method of claim 7 , wherein said programmable input/output block comprises at least one converter unit having a converter input coupled to said asynchronous logic element outputs to receive said operation results, the at least one converter unit providing said operation results synchronously at a converter unit output.

9. The method of claim 7 , wherein said programmable input/output block comprises at least one converter unit having a converter input coupled to said asynchronous logic element outputs to receive said operation results, the at least one converter unit providing said operation results asynchronously at a converter unit output.

10. The method of claim 9 , wherein said converter unit output is coupled to a buffer register, said buffer register being configured to accumulate and store said operation results, and said buffer register including a control input for stepped operation of said buffer register such that said operation results are provided to said external circuits in a stepped manner to enable troubleshooting of said integrated circuit.

11. The method of claim 1 , wherein said asynchronous logic elements further include a plurality of reconfigurable logic blocks (RLBs), each RLB comprising at least one logic cluster, the at least one logic cluster comprising at least one look-up table (LUT), and the at least one LUT including inputs comprising said asynchronous logic element inputs.

12. An Electronic Design Automation (EDA) tool that operates to configure an asynchronous reconfigurable logic fabric, the EDA tool being programmable to perform operations comprising:

characterizing one or more asynchronous dataflow representations for the asynchronous reconfigurable logic fabric, the asynchronous dataflow representations being selected from a group comprising at least one of merge, copy, function, split, sink, source, or initiate; and

configuring an embedded array comprising asynchronous logic elements that include one or more of the asynchronous dataflow representations, said asynchronous logic elements being programmable to carry out logic operations on signals provided at asynchronous logic element inputs and to asynchronously provide operation results at asynchronous logic element outputs, and said asynchronous logic elements include at least one multiplier unit coupled to at least one memory unit.

13. The EDA tool of claim 12 , wherein said at least one multiplier unit and said at least on memory unit are directly coupled.

14. The EDA tool of claim 12 , wherein said at least one multiplier unit and said at least one memory unit are coupled by an interconnecting grid.

15. The EDA tool of claim 12 , wherein said at least one multiplier unit and said at least one memory unit are coupled by a first connection and a second connection comprising respectively a direct connection and an interconnecting grid.

16. The EDA tool of claim 15 , wherein said asynchronous reconfigurable logic fabric further comprises at least one programmable connection unit for selecting between said direct connection and said interconnecting grid.

17. The EDA tool of claim 12 , wherein said at least one multiplier unit and said at least one memory unit are programmable.

18. The EDA tool of claim 12 , wherein the EDA tool is further configured to perform operations comprising:

configuring a programmable input/output block that couples said asynchronous logic element inputs and said asynchronous logic element outputs to external circuits, said programmable input/output block being programmable for synchronous operation with said external circuits.

19. The EDA tool of claim 18 , wherein said programmable input/output block comprises at least one converter unit having a converter input coupled to said asynchronous logic element outputs to receive said operation results, the at least one converter unit providing said operation results synchronously at a converter unit output.

20. The EDA tool of claim 18 , wherein said programmable input/output block comprises at least one converter unit having a converter input coupled to said asynchronous logic element outputs to receive said operation results, the at least one converter unit providing said operation results asynchronously at a converter unit output.

21. The EDA tool of claim 20 , wherein said converter unit output is coupled to a buffer register, said buffer register being configured to accumulate and store said operation results, and said buffer register including a control input for stepped operation of said buffer register such that said operation results are provided to said external circuits in a stepped manner to enable troubleshooting of said integrated circuit.

22. The EDA tool of claim 12 , wherein said asynchronous logic elements further include a plurality of reconfigurable logic blocks (RLBs), each RLB comprising at least one logic cluster, the at least one logic cluster comprising at least one look-up table (LUT), and the at least one LUT including inputs comprising said asynchronous logic element inputs.