Transaction level model synthesis

1. A computer implemented method comprising:

receiving a transaction level model description of an integrated circuit;

generating a synthesizable subset of the transaction level model description from the transaction level model description, the synthesizable subset including a communication portion and a behavioral portion, the communication portion independently synthesizable;

automatically converting function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description;

automatically generating interface logic in the synthesizable subset of the register transfer level description, the interface logic comprising an interface between a bus interface and the signal accesses, the interface logic including combinational logic of a signal generator and buffer registers; and

storing in a computer readable medium the register transfer level description including said signal accesses and the interface logic between the bus interface and said signal accesses.

2. The method of claim 1 , wherein the buffer registers are modeled as clock methods and the combination logic is modeled as a method sensitive to its inputs.

3. The method of claim 2 , wherein the buffer registers are inferred and one or more buffer registers store protocol content to implement a cross-reference to another transfer belonging to a same transaction.

4. The method of claim 1 , further comprising inferring said buffer registers in the register transfer level description from the transaction level model description.

5. The method of claim 4 , further comprising storing protocol content in said buffer registers.

6. The method of claim 5 , wherein said protocol content comprises an address.

7. The method of claim 1 , further comprising replacing event sensitivity in the transaction level model description with clock edge sensitivity in the register transfer level description.

8. The method of claim 1 wherein said interface logic is operable to generate signals that are accessible by the signal accesses.

9. The method of claim 8 , wherein said combinational logic is operable to generate said signals.

10. The method of claim 8 , wherein said interface logic is operable to generate said signals based on local state.

11. The method of claim 1 , further comprising replacing a port object in the transaction level model description with a protocol pin interface in the register transfer level description.

12. The method of claim 1 , wherein the transaction level model description comprises a description of a peripheral component.

13. The method of claim 1 , further comprising activating signal drivers in the register transfer level description.

14. A non-transitory computer readable medium comprising stored instructions to convert a transaction level model to a register transfer level that when executed causes or more processors to:

receive a transaction level model description of an integrated circuit;

generate a synthesizable subset of the transaction level model description from the transaction level model description, the synthesizable subset including a communication portion and a behavioral portion, the communication portion independently synthesizable;

automatically convert function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description;

automatically generate interface logic in the synthesizable subset of the register transfer level description, the interface logic comprising an interface between a bus interface and the signal accesses, the interface logic including combinational logic of a signal generator and buffer registers; and

store in the register transfer level description including said signal accesses and the interface logic between the bus interface and said signal accesses.

15. The computer readable medium of claim 14 , wherein the buffer registers are modeled as clock methods and the combination logic is modeled as a method sensitive to its inputs.

16. The computer readable medium claim 15 , wherein the buffer registers are inferred and one or more buffer registers store protocol content to implement a cross-reference to another transfer belonging to a same transaction.

17. The computer readable medium of claim 14 , further comprising instructions that cause the processors to infer said buffer registers in the register transfer level description from the transaction level model description.

18. The computer readable medium of claim 17 , further comprising storing protocol content in said buffer registers.

19. The computer readable medium of claim 18 , wherein said protocol content comprises an address.

20. The computer readable medium of claim 14 , further comprising instructions that cause the processors to replace event sensitivity in the transaction level model description with clock edge sensitivity in the register transfer level description.