IP Library Granted Patent US 8,952,411
Granted Patent B2
US 8,952,411 · App. 14/080,805 · Granted Feb 10, 2015

Light emitting diode

Inventors: Yi-Keng Fu (Hsinchu County, TW); Rong Xuan (New Taipei, TW); Hsun-Chih Liu (Taipei, TW)
Assignee: Industrial Technology Research Institute
H01L33/12H01L33/20
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Quick Facts
Patent No.
US 8,952,411
App. No.
14/080,805
Granted
Feb 10, 2015
Kind
B2
Abstract

A light emitting diode device may include a carrier, a p-type and n-type semiconductor layers, an active layer, a first electrode and a second electrode is provided. The carrier has a growth surface and at least one nano-patterned structure on the growth surface, in which the carrier includes a substrate and a semiconductor capping layer disposed between the substrate and the n-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer are located over the growth surface of the carrier. The active layer is located between the n-type and p-type semiconductor layers, in which a wavelength λ of light emitted by the active layer is 222 nm≦λ≦405 nm, and a defect density of the active layer is less than or equal to 5×10 10 /cm 2 . The first and second electrodes are respectively connected to the n-type and p-type semiconductor layers. A carrier for carrying a semiconductor layer is also provided.

Claims (23)

1. A light emitting diode (LED) device, comprising:

a carrier, having a growth surface and at least one nano-patterned structure on the growth surface, wherein the carrier comprises a substrate and a semiconductor capping layer;

an n-type semiconductor layer and a p-type semiconductor layer, located over the growth surface of the carrier, wherein the semiconductor capping layer is disposed between the substrate and the n-type semiconductor layer;

an active layer located between the n-type semiconductor layer and the p-type semiconductor layer, wherein a wavelength λ of light emitted by the active layer is 222 nm≦λ≦405 nm, and a defect density of the active layer is less than or equal to 5×10 10 /cm 2 ; and

a first electrode and a second electrode, respectively connected to the n-type semiconductor layer and the p-type semiconductor layer.

2. The LED device according to claim 1 , wherein a defect density of the semiconductor capping layer is less than or equal to 1×10 10 /cm 2 .

3. The LED device according to claim 1 , the at least one nano-patterned structure is on a surface of the substrate, and the semiconductor capping layer covers and is in contact with the at least one nano-patterned structure.

4. The LED device according to claim 1 , wherein the substrate has a plane surface, the semiconductor capping layer covers the plane surface, the at least one nano-patterned structure is on a surface of the semiconductor capping layer, and the n-type semiconductor layer covers and is in contact with the at least one nano-patterned structure.

5. The LED device according to claim 1 , wherein the substrate has a patterned surface, the semiconductor capping layer covers the patterned surface, the at least one nano-patterned structure is on a surface of the semiconductor capping layer, and the n-type semiconductor layer covers and is in contact with the at least one nano-patterned structure.

6. The LED device according to claim 1 , wherein a thickness of the semiconductor capping layer is less than or equal to 10 μm, and ranges from 1 μm to 4 μm.

7. The LED device according to claim 1 , wherein a material of the semiconductor capping layer comprises gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium gallium nitride (InGaN) or a combination thereof.

8. The LED device according to claim 1 , wherein the at least one nano-patterned structure comprises a plurality of mesas, and a recess is formed between two adjacent mesas.

9. The LED device according to claim 8 , wherein the mesas of the at least one nano-patterned structure are arranged regularly.

10. The LED device according to claim 8 , wherein the mesas of the at least one nano-patterned structure are arranged randomly.

11. The LED device according to claim 8 , wherein a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.

12. The LED device according to claim 8 , wherein a dimension w 1 of the mesa and a dimension w 2 of the recess satisfy the following relationship:

0.0125 ≦[w 1 /w 2 ]≦80.

13. The LED device according to claim 1 , wherein a plurality of voids are formed above the recesses or above the mesas between the substrate and the n-type semiconductor layer.

14. The LED device according to claim 13 , wherein each of the voids has a refraction coefficient n2, the substrate has a refraction coefficient n1 and the semiconductor capping layer has a refraction coefficient n3, where n3>n2>n1.

15. The LED device according to claim 8 , further comprising:

a mask layer, covering sidewalls of each mesa and a bottom surface of each recess between the two adjacent mesas.

16. The LED device according to claim 15 , wherein a thickness of the mask layer ranges from 0.1 μm to 2 μm.

17. The LED device according to claim 15 , wherein a material of the mask layer comprises silicon dioxide, silicon nitride or silicon oxynitride.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2022
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: LITE-ON TECHNOLOGY CORPORATION
Reel/Frame 061729/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2014
From: FU, YI-KENG; XUAN, RONG; LIU, HSUN-CHIH
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 032151/0544 →
Continuity (2)
Provisional Application 61727090 · Nov 15, 2012
Related Publication 20140131732A1 · May 15, 2014