Three dimensional stacked nonvolatile semiconductor memory
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.
1. A nonvolatile semiconductor memory comprising:
a semiconductor substrate;
a memory cell array including a first block and a second block disposed above the semiconductor substrate adjacent to each other in a first direction; and
a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction,
wherein the first and second blocks include at least two conductive layers arranged in a third direction perpendicular to the first and second directions above the semiconductor substrate, bit lines disposed above the at least two conductive layers extending in the first direction, and columnar semiconductors passing through the at least two conductive layers, and
wherein a source diffusion layer is disposed in the semiconductor substrate under the first and second blocks and extends in an in-plane direction which is formed by the first direction and the second direction,
a conductive element, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above the at least two conductive layers, the conductive element extends in the third direction and is interposed between ends of the at least two conductive layers of the first block and ends of the at least two conductive layers of the second block, and
the columnar semiconductors in the first and second blocks have lower ends connected to the source diffusion layer and upper ends connected to the bit lines.
2. The memory according to claim 1 , wherein the conductive element is comprised of a columnar semiconductor having the same structure as those of the columnar semiconductors.
3. The memory according to claim 1 , further comprising a dummy bit line and a connection member disposed alongside the bit lines, wherein the source line is disposed above the bit lines as well as connected to the upper end of the conductive element through the connection member, and the dummy bit line is placed in a floating state.
4. The memory according to claim 1 , wherein the source line is disposed alongside the bit lines, and the bit lines and the source lines extend in the first direction together.
5. The memory according to claim 1 , wherein the source line is connected to a common source lines disposed above the bit lines and the source line.
6. The memory according to claim 1 , wherein one end in the second direction of the at least two conductive layers is formed stepwise.
7. The memory according to claim 6 , wherein one end in the second direction of each of the at least two conductive layers is connected to an interconnect line located above the at least two conductive layers through the conductive element.
8. The memory according to claim 7 , wherein the interconnect line is connected to the first driver.
9. The memory according to claim 6 , wherein one end in the second direction of each of the at least two conductive layers excluding the uppermost layer is connected to an interconnect line located above the at least two conductive layers through a contact plug.
10. The memory according to claim 9 , wherein the interconnect line is connected to the first driver.
11. The memory according to claim 9 , wherein the other end in the second direction of the uppermost layer of the at least two conductive layers is connected to an interconnect line located above the at least two conductive layers through a contact plug.
12. The memory according to claim 1 , wherein the memory cell and the select gate transistor comprise a NAND cell unit.
13. The memory according to claim 1 , wherein the semiconductor substrate has the source diffusion layer, and the columnar semiconductors are connected to the source diffusion layer.
14. The memory according to claim 13 , wherein the source diffusion layer is common to the first and second blocks.
15. The memory according to claim 1 , wherein at least two of the columnar semiconductors in the first and second blocks are connected to one of the bit lines and pass through the at least two conductive layers.
16. A nonvolatile semiconductor memory comprising:
a semiconductor substrate;
a memory cell array including a first block and a second block disposed above the semiconductor substrate adjacent to each other in a first direction; and
a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction,
wherein the first and second blocks include at least three conductive layers arranged in a third direction perpendicular to the first and second directions above the semiconductor substrate, bit lines disposed above the at least three conductive layers extending in the first direction, and columnar semiconductors passing through the at least three conductive layers,
wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in the second direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line, and remaining conductive layers excluding the uppermost layer of the at least three conductive layers have a plate shape whose width in the first direction is larger than the width in the first direction of the first select gate lines,
wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively and memory cells are comprised of the word line and the columnar semiconductors, respectively, and
wherein a source diffusion layer is disposed in the semiconductor substrate under the first and second blocks and extends in an in-plane direction which is formed by the first direction and the second direction,
a conductive element, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above the at least three conductive layers, the conductive element extends in the third direction and is interposed between ends of at least two conductive layers of the first block and ends of at least two conductive layers of the second block, and
the columnar semiconductors in the first and second blocks have lower ends connected to the source diffusion layer and upper ends connected to the bit lines.
17. The memory according to claim 16 , wherein the conductive element is comprised of a columnar semiconductor which has the same structure as the columnar semiconductors passing through the at least three conductive layers.
18. The memory according to claim 16 , wherein the source line is connected to a common source line which is provided above the bit lines and the source line.
19. The memory according to claim 16 , wherein the memory cell and the select gate transistor comprise a NAND cell unit.
20. The memory according to claim 16 , wherein the semiconductor substrate has the source diffusion layer, and the columnar semiconductors are connected to the source diffusion layer.
21. The memory according to claim 16 , wherein at least two of the columnar semiconductors in the first and second blocks are connected to one of the bit lines and pass through the at least two conductive layers.
22. A nonvolatile semiconductor memory comprising:
a semiconductor substrate; and
a memory cell array including a first block and a second block disposed above the semiconductor substrate adjacent to each other in a first direction,
wherein the first and second blocks include at least two conductive layers arranged in a third direction perpendicular to the first and second directions above the semiconductor substrate, bit lines disposed above the at least two conductive layers extending in the first direction, and columnar semiconductors passing through the at least two conductive layers,
wherein the memory cell and the select gate transistor comprise a NAND cell unit and the NAND cell unit is connected between the bit line and the source line which are provided above the at least two conductive layers and are insulated from the at least two conductive layers, and the columnar semiconductors in the first and second blocks having lower ends connected to a source diffusion layer of the NAND cell unit and upper ends connected to the bit lines, the source diffusion layer extending in an in-plane direction which is formed by the first direction and a second direction perpendicular to the first direction,
a conductive element, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above the at least two conductive layers, the conductive element extends in the third direction and is interposed between ends of the at least two conductive layers of the first block and ends of the at least two conductive layers of the second block, and
the columnar semiconductors in the first and second blocks have lower ends connected to the source diffusion layer and upper ends connected to the bit lines.
23. The memory according to claim 22 , wherein at least two of the columnar semiconductors in the first and second blocks are connected to one of the bit lines and pass through the at least two conductive layers.