Electrostatic discharge circuit using inductor-triggered silicon-controlled rectifier

1. An electrostatic discharge (ESD) protection circuit comprising:

a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode, wherein the anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material; and

an inductor electrically coupled between the anode and the second P-type semiconductor material wherein an electrical path from the anode to the inductor to the second P-type semiconductor material excludes the first and second N-type semiconductor materials or between the cathode and the first N-type semiconductor material wherein the electrical path from the cathode to the inductor to the first N-type semiconductor material excludes the first and second P-type semiconductor materials.

2. The ESD protection circuit of claim 1 , further comprising at least one diode electrically coupled in series with the inductor between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material.

3. The ESD protection circuit of claim 1 , further comprising a PMOS transistor electrically coupled in series with the inductor between the anode and the second P-type semiconductor material or between the first N-type semiconductor material and the cathode.

4. The ESD protection circuit of claim 3 , further comprising an electrostatic discharge (ESD) detection circuit that is coupled to a gate of the PMOS transistor.

5. The ESD protection circuit of claim 1 , further comprising an NMOS transistor electrically coupled in series with the inductor between the anode and the second P-type semiconductor material or between the first N-type semiconductor material and the cathode.

6. The ESD protection circuit of claim 5 , further comprising an electrostatic discharge (ESD) detection device that is coupled to a gate of the NMOS transistor.

7. The ESD protection circuit of claim 1 , wherein the inductor is electrically coupled between the anode and the second P-type semiconductor material.

8. The ESD protection circuit of claim 1 , wherein the inductor is electrically coupled between the cathode and the first N-type semiconductor material.

9. A structure comprising:

a P substrate;

an N-Well and a P-well that is positioned above the P substrate;

a P+ semiconductor material that is positioned in the N-well;

an N+ semiconductor material that is positioned in the P-well;

an alternating arrangement of the P+ semiconductor material, the N-Well, the P-Well and the N+ semiconductor material; and

an inductor electrically coupled between the P+ semiconductor material and the P-Well wherein an electrical path from the anode to the inductor to the second P-type semiconductor material excludes the first and second N-type semiconductor materials or between the N-Well and the N+ semiconductor material wherein the electrical path from the N-Well to the inductor to the N+ semiconductor material excludes the P-Well and the P+ semiconductor material.

10. The structure of claim 9 , further comprising at least one diode electrically coupled in series with the inductor between the P+ semiconductor material and the P-Well or between the N-Well and the N+ semiconductor material.

11. The structure of claim 9 , further comprising a PMOS transistor electrically coupled in series with the inductor between the P+ semiconductor material and the P-Well or between the N-Well and the N+ semiconductor material.

12. The structure of claim 11 , further comprising an electrostatic discharge (ESD) detection circuit that is coupled to a gate of the PMOS transistor.

13. The structure of claim 9 , further comprising an NMOS transistor electrically coupled in series with the inductor between the P+ semiconductor material and the P-Well or between the N-Well and the N+ semiconductor material.

14. The structure of claim 13 , further comprising an electrostatic discharge (ESD) detection device that is coupled to a gate of the NMOS transistor.

15. The structure of claim 9 , wherein the inductor is electrically coupled between the P+ semiconductor material and the P-Well.

16. The structure of claim 9 , wherein the inductor is electrically coupled between the N-Well and the N+ semiconductor material.

17. A radio frequency (RF) receiver comprising:

an antenna for reception of RF signals;

an electrostatic discharge (ESD) protection circuit having an input for receiving the RF signals, wherein the ESD protection circuit diverts an electrostatic discharge received by the RF receiver away from other components of the RF receiver, wherein the ESD protection circuit includes:

a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode, wherein the anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material; and

an inductor electrically coupled between the anode and the second P-type semiconductor material wherein an electrical path from the anode to the inductor to the second P-type semiconductor material excludes the first and second N-type semiconductor materials or between the cathode and the first N-type semiconductor material wherein the electrical path from the cathode to the inductor to the first N-type semiconductor material excludes the first and second P-type semiconductor materials.

18. The RF receiver of claim 17 , wherein the other components of the RF receiver include at least one of the following:

an amplifier that receives and amplifies the RF signals,

a band-pass filter that receives the amplified RF signals, and

a mixer that receives and mixes the filtered RF signals with local oscillator signals, wherein the mixer sends the mixed signals to an intermediate frequency section of the RF receiver.

19. The RF receiver of claim 17 , wherein the inductor is electrically coupled between the anode and the second P-type semiconductor material.

20. The RF receiver of claim 17 , wherein the inductor is electrically coupled between the cathode and the first N-type semiconductor material.