IP Library Granted Patent US 8,954,821
Granted Patent B2
US 8,954,821 · App. 13/512,000 · Granted Feb 10, 2015

Memory device having address and command selectable capabilities

Inventor: Ferdinando Bedeschi (Biassono, IT)
Assignee: MicronTechnology, Inc.
G11C8/12G06F11/1068G11C29/42G06F12/0223
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Quick Facts
Patent No.
US 8,954,821
App. No.
13/512,000
Granted
Feb 10, 2015
Kind
B2
Abstract

Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.

Claims (32)

1. A method comprising:

receiving at least one of an address for storing and a command to store information;

selecting a particular partition from among two or more partitions in a memory array to store said information, wherein stored information in each of said two or more partitions has a corresponding reliability and wherein said particular partition is selected based upon said reliabilities of said stored information in said two or more partitions; and

operating a particular error correcting code (ECC) algorithm for said selected particular partition, wherein a capacity to correct errors of said particular error correcting code (ECC) algorithm is selected based, at least in part, on said reliabilities of said stored information in said two or more partitions.

2. The method of claim 1 , further comprising applying a particular sense amplifier circuit and a particular write circuit based, at least in part, on said selected particular partition.

3. The method of claim 2 , further comprising configuring said particular sense amplifier circuit and said particular write circuit based, at least in part, on said at least one of said address and said command.

4. The method of claim 1 , further comprising selecting said particular partition based, at least in part on a type of said information.

5. The method of claim 4 , wherein said type of said information comprises at least one of a program code, operating system code, and data.

6. The method of claim 1 , wherein said selecting is further based at least in part on said at least one of said address and said command.

7. The method of claim 1 , further comprising configuring said particular ECC algorithm based, at least in part, on said at least one of said address and said command.

8. The method of claim 1 , further comprising storing at least a portion of said information in said particular partition using programming pulses having attributes based, at least in part, on said at least one of said address and said command.

9. The method of claim 8 , wherein said attributes comprise at least one of a type of operations of a program algorithm, type of sequences of said program algorithm, verify levels, verify number, program pulse number and order, reset pulse amplitude, set pulse length, set pulse peak height, and set pulse shape.

10. The method of claim 1 , further comprising selecting a rate at which to write said information based, at least in part, on said at least one of said address and said command.

11. The method of claim 10 , further comprising selecting a rate at which to write said information based, at least in part, on a differentiation of program algorithms.

12. An apparatus comprising:

a controller to:

receive at least one of an address for storing and a command to store information;

select a particular partition from among two or more partitions in a memory array to store said information, wherein stored information in each of said two or more partitions has a corresponding reliability, and wherein said particular partition is selected based upon said reliabilities of said stored information in said two or more partitions; and

operate a particular error correcting code (ECC) algorithm for said selected particular partition, wherein a capacity to correct errors of said particular error correcting code (ECC) algorithm is selected based, at least in part, on said reliabilities of said stored information in said two or more partitions.

13. The apparatus of claim 12 , said controller to apply a particular sense amplifier circuit and write circuit based, at least in part, on said selected particular partition.

14. The apparatus of claim 13 , further comprising configuring said particular sense amplifier circuit and said write circuit based, at least in part, on said at least one of said address and said command.

15. The apparatus of claim 12 , said controller to select said particular partition based, at least in part on a type of said information.

16. The apparatus of claim 15 , wherein said type of said information comprises at least one of a program code, operating system code, and data.

17. The apparatus of claim 12 , said controller to configure said particular ECC algorithm based, at least in part, on said at least one of said address and said command.

18. A system comprising:

a memory device comprising an array of memory cells, said memory device further comprising a memory controller to:

receive at least one of an address for storing and a command to store information;

select a particular partition from among two or more partitions in a memory array to store said information, wherein stored information in each of said two or more partitions has a corresponding reliability, and wherein said particular partition is selected based upon said reliabilities of said stored information in said two or more partitions; and

operate a particular error correcting code (ECC) algorithm for said selected particular partition, wherein a capacity to correct errors of said particular error correcting code (ECC) is selected based, at least in part, on said reliabilities of said stored information in said two or more partitions; and

a processor to host one or more applications and to initiate said at least one of said address and said command to said memory controller to provide access to said memory cells in said memory cell array.

19. The system of claim 18 , said memory controller to apply a particular sense amplifier circuit based, at least in part, on said selected particular partition.

20. The system of claim 18 , said memory controller to select said particular partition based, at least in part on a type of said information.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2012
From: BEDESCHI, FERDINANDO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 028969/0799 →
Continuity (1)
Related Publication 20130007564A1 · Jan 3, 2013