Method and apparatus for optimizing reference voltages in a nonvolatile memory

1. A system comprising:

a divider module configured to

select a voltage range in which to adjust a reference voltage used to read memory cells of a nonvolatile memory, and

divide the voltage range into a plurality of bins, wherein each of the bins is defined by a pair of voltages;

a read module configured to perform a plurality of read operations by applying, to the memory cells, the voltages defining the bins;

a counting module configured to generate, in each of the read operations, counts of a number of memory cells having threshold voltages in each of the bins; and

a reference voltage setting module configured to adjust, based on the counts, the reference voltage to a voltage selected from one or more voltages associated with the bins.

2. The system of claim 1 , wherein the reference voltage setting module is configured to adjust the reference voltage to a voltage associated with one of the bins having a smallest one of the counts.

3. The system of claim 1 , further comprising:

a voltage generator configured to generate the voltages defining the bins and to apply the voltages to the memory cells during the read operations;

a sensing module configured to sense currents through the memory cells in response to applying each of the voltages to the memory cells; and

a threshold voltage module configured to determine threshold voltages of the memory cells based on the currents.

4. The system of claim 1 , wherein the counting module is configured to generate:

a first count of memory cells having threshold voltages less than a first one of the voltages in response to applying the first one of the voltages to the memory cells during a first one of the read operations,

a second count of memory cells having threshold voltages less than a second one of the voltages in response to applying the second one of the voltages to the memory cells during a second one of the read operations, and

generate one of the counts based on a difference between the first count and the second count.

5. The system of claim 1 , wherein the counting module is configured to generate the counts by counting a number of 1's or 0's detected during each of the read operations.

6. The system of claim 1 , wherein the reference voltage is one of seven reference voltages, wherein Gray mapping is used to map states of the memory cells, and wherein in response to each of the memory cells storing 3-bits, the read module is configured to read:

a most significant bit page comprising most significant bits of the memory cells when the reference voltage being adjusted is fourth of the seven reference voltages;

a least significant bit page comprising least significant bits of the memory cells when the one of the reference voltage being adjusted is one of first, third, fifth, and seventh of the seven reference voltages; and

a central significant bit page comprising central significant bits of the memory cells when the reference voltage being adjusted is one of second and sixth of the seven reference voltages.

7. The system of claim 1 , wherein:

the memory cells have a threshold voltage distribution; and

the reference voltage setting module is configured to adjust the reference voltage in response to and to compensate for a change in the threshold voltage distribution of the memory cells.

8. The system of claim 1 , wherein the reference voltage setting module is configured to adjust the reference voltage in response to one or more of:

a number of erase/program cycles performed on the memory cells;

a number of read errors detected over a period of time while reading the memory cells; and

a period of time elapsed since a prior adjusting of the reference voltage.

9. The system of claim 1 , wherein the reference voltage setting module is configured to adjust the reference voltage independently of one or more of data stored in the memory cells and an error correcting code used to store data in the memory cells.

10. The system of claim 1 , wherein the read module is configured to read data stored in the memory cells using the adjusted reference voltage.

11. A method comprising:

selecting a voltage range in which to adjust a reference voltage used to read memory cells of a nonvolatile memory;

dividing the voltage range into a plurality of bins, wherein each of the bins is defined by a pair of voltages;

performing a plurality of read operations by applying, to the memory cells, the voltages defining the bins;

generating, in each of the read operations, counts of a number of memory cells having threshold voltages in each of the bins; and

adjusting, based on the counts, the reference voltage to a voltage selected from one or more voltages associated with the bins.

12. The method of claim 11 , further comprising adjusting the reference voltage to a voltage associated with one of the bins having a smallest one of the counts.

13. The method of claim 11 , further comprising:

sensing currents through the memory cells in response to applying each of the voltages to the memory cells; and

determining threshold voltages of the memory cells based on the currents.

14. The method of claim 11 , further comprising:

generating a first count of memory cells having threshold voltages less than a first one of the voltages in response to applying the first one of the voltages to the memory cells during a first one of the read operations,

generating a second count of memory cells having threshold voltages less than a second one of the voltages in response to applying the second one of the voltages to the memory cells during a second one of the read operations, and

generating one of the counts based on a difference between the first count and the second count.

15. The method of claim 11 , further comprising generating the counts by counting a number of 1's or 0's detected during each of the read operations.

16. The method of claim 11 , wherein the reference voltage is one of seven reference voltages, wherein Gray mapping is used to map states of the memory cells, and wherein in response to each of the memory cells storing 3-bits, the method further comprising:

reading a most significant bit page comprising most significant bits of the memory cells when the reference voltage being adjusted is fourth of the seven reference voltages;

reading a least significant bit page comprising least significant bits of the memory cells when the one of the reference voltage being adjusted is one of first, third, fifth, and seventh of the seven reference voltages; and

reading a central significant bit page comprising central significant bits of the memory cells when the reference voltage being adjusted is one of second and sixth of the seven reference voltages.

17. The method of claim 11 , wherein the memory cells have a threshold voltage distribution, the method further comprising adjusting the reference voltage in response to and to compensate for a change in the threshold voltage distribution of the memory cells.

18. The method of claim 11 , further comprising adjusting the reference voltage in response to one or more of:

a number of erase/program cycles performed on the memory cells;

a number of read errors detected over a period of time while reading the memory cells; and

a period of time elapsed since a prior adjusting of the reference voltage.

19. The method of claim 11 , further comprising adjusting the reference voltage independently of one or more of data stored in the memory cells and an error correcting code used to store data in the memory cells.

20. The method of claim 11 , further comprising reading data stored in the memory cells using the adjusted reference voltage.