Bank selection circuit and memory device having the same
A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal.
1. A bank selection circuit comprising:
a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time;
a command decoder configured to decode a latched command and generate a row operation signal;
a bank address latch unit configured to latch a bank address of input addresses at a time earlier than the rising edge of the clock by the setup time;
a row address latch unit configured to latch a row address of the input addresses at the rising edge of the clock;
a bank address decoder configured to decode a latched bank address and generate a bank selection signal;
a bank selection unit configured to receive the row operation signal generated by the command decoder and the bank selection signal generated by the bank address decoder and transfer the row operation signal to a bank selected by the bank selection signal; and
a core area configured to perform an operation corresponding to the row operation signal using a latched row address in the selected bank,
wherein the bank address latch unit is configured to latch the bank address at a time earlier than a time when the row address latch unit latches the row address by the setup time.
2. The bank selection circuit of claim 1 , wherein the command latch unit and the bank address latch unit are formed of a through-type latch.
3. The bank selection circuit of claim 1 , wherein the row address latch unit is formed of an edge trigger-type latch.
4. The bank selection circuit of claim 1 , wherein the bank address latch unit is configured to latch the input bank address at a time substantially equal to a time when the command latch unit latches the input command.
5. The bank selection circuit of claim 1 , wherein the row operation signal includes an active or precharge signal.