IP Library Granted Patent US 8,963,121
Granted Patent B2
US 8,963,121 · App. 13/708,526 · Granted Feb 24, 2015

Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods

Inventors: Vladimir Odnoblyudov (Eagle, ID); Martin F. Schubert (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/04H01L21/78H01L27/156H01L33/0095H01L33/382H01L33/62
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Quick Facts
Patent No.
US 8,963,121
App. No.
13/708,526
Granted
Feb 24, 2015
Kind
B2
Abstract

Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Claims (30)

1. A solid state transducer (SST) die, comprising:

a transducer structure having a first side and a second side opposite the first side, a first semiconductor material at the first side and a second semiconductor material at the second side;

a plurality of first contacts, with individual first contacts electrically coupled to the first semiconductor material;

a plurality of second contacts, with second contacts electrically coupled to the second semiconductor material, the second contacts extending from the first side of the transducer structure to the second semiconductor material;

a plurality of features that separate the transducer structure of the die into a plurality of electrically isolated transducer junctions including at least a first transducer junction and a second transducer junction, wherein the first transducer junction has one of the first contacts and one of the second contacts and the second transducer junction has another of the first contacts and another of the second contacts; and

an interconnect formed between the second contact on the first transducer junction and the exposed first contact on the second transducer junction such that the first and second transducer junctions of the die are electrically connected in series.

2. The SST die of claim 1 further comprising a dielectric material between the interconnect and the first semiconductor material and a plurality of package materials covering the interconnect.

3. The SST die of claim 1 wherein the first contacts and the second contacts are buried, and wherein the SST die further comprises a first external terminal electrically coupled to the first contact of the first transducer junction and a second external terminal electrically coupled to the second contact of the second transducer junction, and wherein the first and second external terminals are configured to connect to a power source.

4. The SST die of claim 1 wherein the transducer structure is a vertical transducer structure having the first contacts and second contacts at the first side, and wherein the SST die is configured to directly attach to an external component.

5. The SST die of claim 1 wherein the transducer structure includes a plurality of high voltage transducer junctions coupled in series.

6. The SST die of claim 1 further comprising a thermal pad at the first side.

7. The SST die of claim 1 wherein the SST die further includes a plurality of additional interconnects between one or more individual first contacts and one or more second contacts.

8. The SST die of claim 1 , further comprising:

a plurality of junctions; and

a third contact connected to the interconnect, the third contact configured to cross-connect to another contact on a second die.

9. The SST die of claim 1 wherein the interconnect is electrically isolated from the first and second semiconductor materials.

10. A high powered light-emitting diode (LED), comprising:

a light-emitting transducer structure having a light-emitting active region positioned between a first semiconductor material at a first side and a second semiconductor material at a second side facing opposite the first side;

a first contact material electrically coupled to the first semiconductor material at the first side of the transducer structure;

a plurality of features that separate the transducer structure of the LED and the first contact material into a plurality of electrically isolated junctions, wherein an individual junction includes a first contact formed from a portion of the first contact material;

a plurality of second contacts electrically connected to the second semiconductor material and extending from the first side of the transducer structure through the light-emitting active region to the second semiconductor material, wherein each junction has one of the second contacts; and

a plurality of junction interconnects, wherein each junction interconnect extends between one of the second contacts of one junction and one of the first contacts of an adjacent junctions such that the plurality of junctions of the LED are electrically coupled in series via the plurality of junction interconnects.

11. The high powered LED of claim 10 , further comprising a passivation material over the first material, wherein a portion of the first contact material is exposed through the passivation material at the first side of the transducer structure.

12. The high powered LED of claim 11 , further comprising a plurality of package materials over the passivation material and the junction interconnects at the first side of the transducer structure.

13. The high powered LED of claim 12 wherein the plurality of package materials includes one or more of a dielectric material, a barrier material, a seed material and a metal substrate.

14. The high powered LED of claim 10 wherein each of the junctions includes a thermal pad at the first side.

15. The SST die of claim 1 further comprising a dielectric material over the first contact, wherein the dielectric material has a plurality of openings configured such that at individual junctions an opening is aligned with one of the first contacts and another opening is aligned with one of the second contacts, and wherein the interconnects are conductive traces formed on the dielectric material such that individual interconnects are electrically coupled to one of the first contacts of an individual junction and one of the second contacts of an adjacent individual junction.

16. The SST die of claim 15 wherein additional passivation material is formed over the interconnects such that the interconnects are encased in the additional passivation material.

17. The high powered LED of claim 10 further comprising a dielectric material over the first contact material, wherein the dielectric material has a plurality of openings configured such that at individual junctions an opening is aligned with one of the first contacts and another opening is aligned with one of the second contacts, and wherein the junction interconnects are electrically coupled to one of the first contacts of an individual junction and one of the second contacts of an adjacent individual junction.

18. The high powered LED of claim 17 wherein additional passivation material is formed over the junction interconnects such that the junction interconnects are encased in the additional passivation material.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2012
From: ODNOBLYUDOV, VLADIMIR; SCHUBERT, MARTIN F.
To: MICRON TECHOLOGY, INC.
Reel/Frame 029429/0398 →
Continuity (1)
Related Publication 20140159063A1 · Jun 12, 2014