Semiconductor devices including WiSX
Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
1. A semiconductor device, comprising:
a stack structure over a substrate, the stack structure including a plurality of alternating tiers of dielectric material and conductive material;
an opening extending into the stack structure to a level adjacent the substrate;
a first poly-silicon channel in a lower portion of the opening adjacent the substrate, and a second poly-silicon channel in an upper portion of the opening; and
WSiX material between and in contact with the first poly-silicon channel and the second poly-silicon channel in the opening, and completely separating the first poly-silicon channel and the second poly-silicon channel.
2. The semiconductor device of claim 1 , wherein the dielectric material comprises tetraethyl ortho silicate (TEOS).
3. The semiconductor device of claim 1 , wherein the dielectric material comprises silicon oxide.
4. The semiconductor device of claim 1 , wherein the opening has a high aspect ratio.
5. The semiconductor device of claim 1 , further including an isolation liner on an inside wall of the opening.
6. The semiconductor device of claim 5 , wherein the isolation liner comprises oxide material.
7. The semiconductor device of claim 5 , wherein the isolation liner comprises nitride material.
8. A semiconductor device, comprising:
a stack structure over a substrate, the stack structure including a plurality of alternating tiers of dielectric material and conductive material;
an opening extending into the stack structure to a level adjacent the substrate;
a first poly-silicon channel in a lower portion of the opening adjacent the substrate, and a second poly-silicon channel in an upper portion of the opening; and
WSiX material between and in contact with the first poly-silicon channel and the second poly-silicon channel in the opening, wherein the stack structure includes a nitride material adjacent a top surface of the stack structure, the top surface located opposite a bottom surface of the stack structure proximate to the substrate.
9. A memory device, comprising:
a substrate; and
a stack structure over the substrate, the stack structure including a plurality of alternating tiers of dielectric material and poly-silicon, and an opening extending into the stack structure to a level adjacent the substrate, the opening including a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, and a second poly-silicon channel formed in an upper portion of the opening,
wherein the opening further includes WSiX material between and in contact with the first poly-silicon channel and the second poly-silicon channel in the opening, and completely separating the first poly-silicon channel and the second poly-silicon channel.