Semiconductor device with reduced miller capacitance and fabrication method thereof
A semiconductor power device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth deeper than the junction depth in the ion well; a gate oxide layer in the gate trench; a gate embedded the gate trench; and a pocket doping region in the epitaxial layer. The pocket doping region is adjacent to and covers at least a corner of the gate trench.
1. A power semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
an epitaxial layer on the semiconductor substrate;
an ion well having a second conductivity type in the epitaxial layer, wherein the ion well has a junction depth;
a gate trench in the epitaxial layer, wherein a depth of the gate trench is greater than the junction depth of the ion well;
a gate oxide layer on interior surface of the gate trench;
a gate within the gate trench; and
at least a pocket doping region having the second conductivity type within the epitaxial layer and being situated directly under a bottom surface of the gate trench, wherein the pocket doping region extends to cover a lower sidewall of the gate trench and wherein the pocket doping region does not completely cover the bottom surface of the gate trench.
2. The power semiconductor device according to claim 1 further comprising a source doping region at a surface of the epitaxial layer and adjacent to the gate trench.
3. The power semiconductor device according to claim 2 wherein the source doping region has the first conductivity type.
4. The power semiconductor device according to claim 1 wherein the first conductivity type is N type and the second conductivity type is P type.
5. The power semiconductor device according to claim 1 wherein the epitaxial layer has the first conductivity type.
6. The power semiconductor device according to claim 1 wherein the pocket doping region traverses a junction between the ion well and the epitaxial layer.
7. The power semiconductor device according to claim 1 wherein the pocket doping region has a doping concentration greater than that of the epitaxial layer.
8. The power semiconductor device according to claim 1 wherein the pocket doping region extends to the bottom surface of the gate trench.