Power semiconductor device
A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.
1. A power semiconductor device comprising:
a first conductive type drift layer formed on a first principal surface of a first conductive type silicon carbide semiconductor substrate;
a plurality of second conductive type main cell wells and a plurality of second conductive type sense wells selectively formed on a surface of the drift layer;
a second conductive type sense outer-peripheral well formed to surround the plurality of sense wells on the surface of the drift layer;
a first conductive type main-cell source region selectively formed on the surface of the main cell well;
a first channel region formed on the surface of the main cell well between the main-cell source region and the drift layer;
a first conductive type sense source region selectively formed on the surface of the sense well;
a second channel region formed on the surface of the sense well between the sense source region and the drift layer;
a plurality of second conductive type contact regions selectively formed on a surface as well as an outer periphery and an inner periphery of the sense outer-peripheral well and electrically connected to the sense pad,
a first conductive type capacitor lower electrode region selectively formed in a region surrounded by the surface as well as the outer periphery and the inner periphery of the sense outer-peripheral well;
a gate insulation film formed on the first and second channel regions and on the sense outer-peripheral well;
a gate electrode formed on the gate insulation film;
a source pad electrically connected to the main cell well and the main-cell source region;
a sense pad electrically connected to the sense well and the sense source region as well as the sense outer-peripheral well and the capacitor lower electrode region; and
a drain electrode formed on a second principal surface of the semiconductor substrate.
2. The power semiconductor device according to claim 1 , further comprising:
a MOSFET configured by the sense well, the sense source region, a second channel region, and a gate electrode; and
a capacitor configured by the sense outer-peripheral well, the capacitor lower electrode region, and the gate electrode, wherein the MOSFET and the capacitor have same configurations other than the sense well and the sense outer-peripheral well.
3. The power semiconductor device according to claim 1 , wherein the sense well and the sense outer-peripheral well are simultaneously formed.
4. The power semiconductor device according to claim 1 , wherein the sense outer-peripheral well comprises:
a first sense outer-peripheral well continuously formed in a region having a predetermined depth from a surface of the drift layer; and
a second sense outer-peripheral well having a same shape as the sense well formed in an island shape corresponding to the contact region and the capacitor lower electrode region from the first sense outer-peripheral well to the surface of the drift layer.