Methods of forming non-volatile memory devices including vertical NAND strings
A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
1. A method of forming a Vertical NAND (VNAND) structure comprising:
alternatingly stacking first layers and second layers to form a stack comprising first and second portions, each of which comprises first and second parts;
forming a first mask pattern to cover the first portion and expose the second portion;
etching the second portion using the first mask pattern as an etch mask;
forming a second mask pattern to cover the first parts of the first and second portions and expose the second parts of the first and second portions; and
etching the second parts of the first and second portions using the second mask pattern as an etch mask.
2. The method of claim 1 , wherein the first part of the first portion of the VNAND structure has a thickness greater than a thickness of the first part of the second portion of the VNAND structure.
3. The method of claim 1 , wherein the first part of the first portion of the VNAND structure has a thickness greater than a thickness of the second part of the first portion of the VNAND structure.
4. The method of claim 1 , wherein the first part of the second portion of the VNAND structure has a thickness greater than a thickness of the second part of the second portion of the VNAND structure.
5. The method of claim 1 , wherein the etching the second portion comprises:
forming a first contact portion having a first height and a second contact portion having a second height less than the first height.
6. The method of claim 5 , wherein the etching the second parts comprises:
forming a third contact portion having a third height which is less than the first height and is greater than the second height and a fourth contact portion having a fourth height less than the second height.
7. The method of claim 6 , wherein the second contact portion is disposed between the third contact portion and the fourth contact portion, and the third contact portion is disposed between the first contact portion and the second contact portion.
8. The method of claim 6 , wherein a difference between the first height and the third height is a difference between a second height and the fourth height.
9. The method of claim 6 , wherein the first, the second, the third and the fourth contact portions are arranged along one direction.
10. The method of claim 1 , wherein at least one of the etching steps is performed in such a way that the number of the first and the second layers to be etched is 2n, where n is zero or positive integers.
11. The method of claim 1 , wherein the etching of the second portion using the first mask pattern forms at least one first etched region with a first etch depth, and
the etching of the second parts of the first and second portions using the second mask pattern forms at least one second etched region with a second etch depth,
wherein the first etch depth is different from the second etch depth.
12. The method of claim 11 , wherein one of the first and second etch depths is substantially twice the other.
13. The method of claim 11 , wherein the stack further comprises a cell region, on which a plurality of bit lines are provided.
14. The method of claim 13 , wherein the at least one first etched region comprises a plurality of first etched regions formed equidistant from one of the plurality of the bit lines, and
the at least one second etched region comprises a plurality of second etched regions formed equidistant from another of the plurality of the bit lines.
15. The method of claim 14 , wherein a distance between the first etched regions and a specific one of the bit lines is substantially equal to a distance between the second etched regions and the specific one of the bit lines.
16. The method of claim 13 , wherein the at least one first etched region is formed at a position spaced apart from a specific one of the bit lines by a first distance, and
the at least one second etched region is formed at a position spaced apart from the specific one of the bit lines by a second distance different from the first distance.
17. The method of claim 1 , wherein the etching of the second portion using the first mask pattern is performed to etch n layers of the first layers, and
the etching of the second parts of the first and second portions using the second mask pattern is performed to etch m layers of the first layers,
wherein m is an integer that is different from n.
18. The method of claim 17 , wherein n is an integer of (m+2) or more.
19. The method of claim 17 , wherein n is 2m.