FinFET channel stress using tungsten contacts in raised epitaxial source and drain
Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.
1. A method, comprising:
providing an intermediate semiconductor structure of a FinFET, the structure comprising a semiconductor substrate and at least one fin coupled to the substrate, the at least one fin comprising a source region, a drain region and a channel between the source region and the drain region;
epitaxially growing a semiconductor material on the source region and the drain region;
removing the epitaxially grown semiconductor material;
epitaxially re-growing the semiconductor material on the source region and the drain region, such that a raised source and a raised drain are created;
etching a trench in the raised source and the raised drain; and
creating tungsten contacts in the raised source trench and raised drain trench, wherein the tungsten contacts have a stress different from an inherent stress of tungsten.
2. The method of claim 1 , wherein etching the source trench and the drain trench comprises etching to a depth approximately parallel with a top surface of the at least one fin.
3. The method of claim 1 , wherein etching the source trench and the drain trench comprises etching to a depth below a top surface of the at least one fin by about 10 nm to about 20 nm, wherein a height of the contacts is about 70 nm to about 120nm, and wherein etching below the top surface comprises etching no lower than about 10nm above a bottom surface of the at least one fin.
4. The method of claim 1 , wherein the creating comprises:
lining the trenches with a contact liner; and
filling the lined trenches with tungsten under conditions altering an inherent stress of the tungsten.
5. The method of claim 4 , wherein the stress on the channel is a tensile stress of about 0.5 GPa to about 3 GPa.
6. The method of claim 4 , wherein the stress on the channel is a compressive stress of about −0.5 GPa to about −3 GPa.
7. The method of claim 4 , wherein the stress is tensile, and wherein lining the trenches comprises:
depositing a layer of titanium in the trenches; and
depositing a layer of titanium nitride over the layer of titanium.
8. The method of claim 4 , wherein the stress is compressive, and wherein lining the trenches comprises:
depositing a layer of titanium in the trenches; and
depositing a layer of liner material comprising tungsten over the layer of titanium.
9. The method of claim 1 , wherein the FinFET is p-type, wherein the epitaxially growing comprises epitaxially growing silicon germanium, and wherein the epitaxially regrowing comprises epitaxially regrowing silicon germanium.
10. The method of claim 1 , wherein the FinFET is n-type, wherein the epitaxially growing comprises epitaxially growing silicon phosphide, and wherein the epitaxially regrowing comprises epitaxially regrowing silicon phosphide.
11. A FinFET, comprising:
a semiconductor substrate;
at least one semiconductor fin coupled to the substrate, the at least one fin comprising a source, a drain and a channel between the source and the drain, the channel situated under a gate, wherein the source and the drain are raised and comprise a regrown epitaxial semiconductor material, wherein the re-grown epitaxial semiconductor material comprises a first growth of the epitaxial semiconductor material and a second growth after partial removal thereof; and
a source contact situated in a lined trench in the source and a drain contact situated in a lined trench in the drain, the contacts comprising tungsten and having a stress different from an inherent stress of tungsten, wherein the raised source and drain together with the tungsten contacts exert a desired stress on the channel.
12. The FinFET of claim 11 , wherein the contacts have a height of about 70 nm to about 120 nm, and wherein a bottom surface of the contacts is about 10 nm to about 20 nm below a top surface of the fin.
13. The FinFET of claim 12 , wherein a bottom surface of the contacts approximately coincides with a bottom surface of the gate and a top surface of the fin.
14. The FinFET of claim 11 , wherein the desired stress comprises a compressive stress of about −0.5 GPa to about −3 GPa.
15. The FinFET of claim 11 , wherein the desired stress comprises a tensile stress about 0.5 GPa to about 3 GPa.
16. The FinFET of claim 11 , wherein the liner of the trenches comprises one of a bottom layer of titanium and a top layer of titanium nitride, and a bottom layer of titanium and a top layer comprising tungsten.