IP Library Granted Patent US 8,975,680
Granted Patent B2
US 8,975,680 · App. 13/369,679 · Granted Mar 10, 2015

Semiconductor memory device and method manufacturing semiconductor memory device

Inventor: Yasuhiko Takemura (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/108H01L27/10844H01L27/1156
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Quick Facts
Patent No.
US 8,975,680
App. No.
13/369,679
Granted
Mar 10, 2015
Kind
B2
Abstract

A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4 F 2 at a minimum.

Claims (43)

1. A semiconductor memory device comprising a gain cell, the gain cell comprising:

a read bit line formed in or over a substrate;

a projecting insulator formed over the substrate;

a write word line that is formed on a side surface of the projecting insulator and faces with a gate insulator interposed therebetween;

a semiconductor interposed between the write word line and the side surface of the projecting insulator;

an electrode provided over a top of the projecting insulator; and

a write bit line that is provided over the projecting insulator and is electrically connected to the electrode.

2. The semiconductor memory device according to claim 1 ,

wherein a height of the write word line is greater than or equal to 30% and less than or equal to 90% of a height of the projecting insulator.

3. The semiconductor memory device according to any one of claim 1 , further comprising a driver circuit below the read bit line.

4. The semiconductor memory device according to claim 1 ,

wherein the semiconductor includes a material whose band gap is greater than or equal to 2.5 eV and less than or equal to 4 eV.

5. The semiconductor memory device according to claim 1 ,

wherein the semiconductor includes an oxide semiconductor.

6. A semiconductor memory device comprising a gain cell, the gain cell comprising:

a read bit line formed in or over a substrate;

a first conductive layer;

a write word line that is formed over the first conductive layer;

a semiconductor in contact with the first conductive layer;

a first insulator interposed between the write word line and the semiconductor;

a second conductive layer provided over an upper portion of the semiconductor, the second conductive layer being in contact with the semiconductor;

a read word line that is formed on a side surface of the first conductive layer and faces with a second insulator interposed therebetween; and

a write bit line that is provided over the second conductive layer and is electrically connected to the second conductive layer.

7. The semiconductor memory device according to claim 6 ,

wherein the first conductive layer functions as a memory node of the gain cell.

8. The semiconductor memory device according to claim 6 ,

wherein the first insulator is the same material as the second insulator.

9. The semiconductor memory device according to claim 6 , further comprising a driver circuit below the read bit line.

10. The semiconductor memory device according to claim 6 ,

wherein the semiconductor includes a material whose band gap is greater than or equal to 2.5 eV and less than or equal to 4 eV.

11. The semiconductor memory device according to claim 6 ,

wherein the semiconductor includes an oxide semiconductor.

12. A method of manufacturing a semiconductor memory device comprising a gain cell, comprising the steps of:

forming a read bit line in or over a substrate;

forming a conductive layer over the read bit line;

forming a first insulator over the conductive layer;

forming a conductive film;

forming a write word line over the conductive layer; and

forming a read word line on a side surface of the conductive layer by anisotropically etching the conductive film.

13. The method of manufacturing a semiconductor memory device according to claim 12 ,

wherein the write word line is formed at the step of the forming the read word line.

14. The method of manufacturing a semiconductor memory device according to claim 12 , further comprising the step of:

forming a semiconductor over the conductive layer, the semiconductor being in contact with the conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2012
From: TAKEMURA, YASUHIKO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 027679/0390 →
Priority Claims (1)
JP 2011-031788 · Feb 17, 2011 · national
Continuity (1)
Related Publication 20120213000A1 · Aug 23, 2012