Nonvolatile pipe gate memory device
A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.
1. A nonvolatile memory device comprising:
a pipe insulation layer surrounding a pipe channel hole;
a pipe gate disposed over the pipe insulation layer;
a pair of cell strings each having a columnar cell channel; and
a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole,
wherein the pipe channel includes a first pipe channel surrounding inner side walls and the bottom of the pipe channel hole and a pair of second pipe channels, each coupled the corresponding columnar cell channel,
wherein the pipe gate surrounds the second pipe channels.
2. The nonvolatile memory device of claim 1 wherein the cell strings are separated by a slit having a depth extending to the surface of the pipe gate.
3. The nonvolatile memory device of claim 1 , wherein each of the cell strings comprises:
a charge storage or charge trapping layer surrounding the columnar cell channel; and
an interlayer insulation layer and a gate electrode surrounding the charge storage or charge trapping layer.
4. The nonvolatile memory device of claim 1 , wherein each of the cell strings comprises:
an interlayer insulation layer having a plurality of undercuts, which partially expose the sidewalls of the columnar cell channel, and surrounding the columnar cell channel;
a charge storage or charge trapping layer covering the undercuts; and
a plurality of gate electrodes disposed on the charge storage or charge trapping layer filling the undercuts.
5. The nonvolatile memory device of claim 1 , wherein the pipe insulation layer comprises an oxide layer.
6. The nonvolatile memory device of claim 1 , wherein the pipe gate includes a first conductive layer and each of the cell strings includes a plurality of gate electrodes formed of a second conductive layer different from the first conductive layer.
7. The nonvolatile memory device of claim 6 , the first conductive layer comprises an N+ polysilicon layer, and the second conductive layer comprises a P+ polysilicon layer.
8. The nonvolatile memory device of claim 6 , the first conductive layer comprises a polysilicon layer, and the second conductive layer comprises a metal layer.
9. A nonvolatile memory device comprising:
a first pipe gate surrounding a pipe channel hole;
a second pipe gate disposed over the first pipe gate;
a pair of cell strings each having a columnar cell channel; and
a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole,
wherein the pipe channel includes a first pipe channel formed within the pipe channel hole and a pair of second pipe channels, each coupled to the corresponding columnar cell channel,
wherein the second pipe gate surrounds the second pipe channels,
wherein the first pipe gate and the second pipe gate are commonly coupled to a metal interconnection.
10. The nonvolatile memory device of claim 9 , further comprising:
a passivation layer disposed between the first pipe gate and the second pipe gate.
11. The nonvolatile memory device of claim 10 , wherein the passivation layer comprises a nitride layer or an oxide layer.
12. The nonvolatile memory device of claim 10 , wherein the cell strings are separated by a slit passing through the second pipe gate and having a depth extending to at least the surface of the passivation layer.
13. The nonvolatile memory device of claim 10 , wherein the cell strings are separated by a slit having a depth extending to any one of an interlayer insulation layer formed between the second pipe gate and a gate electrode of each of the cell strings, the second pipe gate, and the passivation layer.
14. The nonvolatile memory device of claim 9 , wherein each of the cell strings comprises:
a charge storage or charge trapping layer surrounding the columnar cell channel; and
an interlayer insulation layer and a gate electrode surrounding the charge storage or charge trapping layer.
15. The nonvolatile memory device of claim 9 , wherein each of the cell strings comprises:
an interlayer insulation layer having a plurality of undercuts, which partially expose the sidewalls of the columnar cell channel, and surrounding the columnar cell channel;
a charge storage or charge trapping layer covering the undercuts; and
a plurality of gate electrodes disposed on the charge storage or charge trapping layer filling the undercuts.
16. The nonvolatile memory device of claim 9 , wherein the first pipe gate and the second pipe gate include a first conductive layer, and each of the cell strings includes a plurality of gate electrodes formed of a second conductive layer different from the first conductive layer.
17. The nonvolatile memory device of claim 16 , wherein the first conductive layer comprises an N+ polysilicon layer, and the second conductive layer comprises a P+ polysilicon layer.