Memory read apparatus and methods
Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.
1. A method comprising:
raising an electrical potential of a plurality of access lines to a raised electrical potential, each access line associated with a charge storage device;
lowering the electrical potential of a selected one of the access lines; and
sensing a state of the charge storage device associated with the selected access line while the electrical potential of the selected access line is being lowered.
2. The method of claim 1 , wherein each access line is adjacent to at least one of the other access lines.
3. The method of claim 1 , wherein lowering the electrical potential of a selected one of the access lines further comprises lowering the electrical potential of the selected access line to a ground voltage.
4. The method of claim 1 , wherein lowering the electrical potential of a selected one of the access lines further comprises lowering the electrical potential of the selected access line by voltage increments.
5. The method of claim 1 , wherein the charge storage device associated with the selected access line is a multilevel charge storage device.
6. The method of claim 1 , further comprising latching data representing a state of the charge storage device associated with the selected access line for each increment of change of the electrical potential of the selected access line.
7. The method of claim 1 , wherein the access lines and the charge storage devices are associated with a pillar comprising semiconductor material.
8. A method comprising:
switching on a plurality of charge storage devices associated with a first pillar comprising semiconductor material;
incrementally reducing an electrical potential of a control gate of a selected one of the charge storage devices; and
sensing an electrical potential of the first pillar while the electrical potential of the control gate is being reduced to determine the electrical potential of the control gate when the selected charge storage device is switched off.
9. The method of claim 8 , further comprising switching on a drain select gate associated with the first pillar to couple the first pillar to a data line.
10. The method of claim 9 , further comprising switching off a drain select gate associated with a second pillar to substantially electrically isolate the second pillar from the data line.
11. The method of claim 10 , further comprising switching on a source select gate associated with the first pillar and a source select gate associated with the second pillar to couple the first pillar and the second pillar to a common source line.
12. The method of claim 8 , further comprising reducing the electrical potential of the control gate of the selected charge storage device in response to each edge of a clock signal.
13. The method of claim 12 , further comprising latching data representing the electrical potential of the first pillar in response to each edge of the clock signal.
14. The method of claim 8 , wherein switching on a plurality of charge storage devices associated with a first pillar further comprises raising an electrical potential of a control gate of each of the plurality of charge storage devices associated with the first pillar.
15. A method comprising:
switching on a charge storage device associated with a pillar comprising semiconductor material;
reducing an electrical potential of a control gate of the charge storage device; and
sensing an electrical potential of the pillar while the electrical potential of the control gate is being reduced to determine the electrical potential of the control gate when the charge storage device is switched off.
16. The method of claim 15 , wherein reducing an electrical potential of a control gate further comprises reducing the electrical potential of the control gate of the charge storage device by voltage increments.
17. The method of claim 15 , wherein reducing an electrical potential of a control gate further comprises reducing the electrical potential of the control gate of the charge storage device to a ground voltage.
18. A method comprising:
switching on a plurality of first charge storage devices associated with a first pillar comprising semiconductor material and switching on a plurality of second charge storage devices associated with a second pillar comprising semiconductor material;
switching on a first source select gate associated with the first pillar and a second source select gate associated with the second pillar to couple the first pillar and the second pillar to a common source;
switching on a first drain select gate associated with the first pillar and a second drain select gate associated with the second pillar to couple the first pillar and the second pillar to a data line;
switching off the second drain select gate associated with the second pillar to substantially electrically isolate the second pillar from the data line;
incrementally lowering an electrical potential of a first control gate of a selected one of the first charge storage devices and a second control gate of a selected one of the second charge storage devices; and
sensing the data line while the electrical potential of the first control gate and the second control gate is being lowered to determine the electrical potential of the first control gate when the selected first charge storage device is switched off.
19. The method of claim 18 , wherein incrementally lowering an electrical potential of the first control gate comprises lowering the electrical potential of the first control gate and the second control gate in response to each edge of a clock signal until a particular level of the electrical potential of the first control gate and the second control gate is established.
20. The method of claim 19 , further comprising changing a value of a digital signal for each increment of change of the electrical potential of the first control gate and the second control gate, and wherein sensing the data line comprises latching a current value of the digital signal responsive to a change in conduction of the selected first charge storage device.
21. The method of claim 18 , wherein switching on a plurality of charge storage devices associated with a pillar further comprises raising an electrical potential of a control gate of each of the plurality of first charge storage devices associated with the first pillar and raising an electrical potential of a control gate of each of the plurality of second charge storage devices associated with the second pillar.
22. The method of claim 18 , further comprising switching off a third drain select gate associated with a third pillar to substantially electrically isolate the third pillar from the data line, a plurality of third charge storage devices associated with the third pillar.
23. The method of claim 22 , further comprising switching off a third source select gate associated with the third pillar to substantially electrically isolate the third pillar from the common source.