Ultra-high voltage N-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same
An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.
1. A method for manufacturing ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device, at least comprising:
providing a substrate of P-type material;
forming a first high-voltage N-well (HVNW) region in a portion of the substrate;
forming a second HVNW region in another portion of the substrate, wherein the second HVNW region is disposed at a high-side operation region of the substrate;
forming at least two p-wells (PWs) separately in a region for PWs, the region for PWs adjacent to the first and second HVNW regions;
forming a source and bulk p-well (PW) adjacent to one side of the first HVNW region;
forming a P-Top layer within the first HVNW region; and
forming an n-type implant layer on the P-Top layer.
2. The method according to claim 1 , wherein the P-Top layer and the n-type implant layer are formed by ion implant or doping.
3. The method according to claim 1 , further comprising:
forming a source and a bulk in the source and bulk PW;
forming a gate extended from the source and bulk PW to a portion of the first HVNW region; and
forming a drain within another portion of the first HVNW region that is opposite to the gate, wherein the P-Top layer and the n-type implant layer are positioned between the drain and the source and bulk PW.
4. The method according to claim 3 , further comprising growing a field oxide (FOX) at the first HVNW region and on the n-type implant layer, wherein the gate is extended from the source and bulk PW to a portion of the FOX.
5. The method according to claim 3 , further comprising growing a field oxide (FOX) at the first HVNW region, and the P-Top layer and the n-type implant layer formed under the FOX after growing the FOX, wherein the gate is extended from the source and bulk PW to a portion of the FOX.
6. The method according to claim 1 , further comprising:
forming an inter-layer dielectric (ILD) layer on the substrate; and
forming a first patterned metal layer on the ILD layer, and a portion of the first patterned metal layer over-passing the region for PWs for high-voltage interconnection.
7. The method according to claim 6 , further comprising
forming an inter-metal dielectric (IMD) layer on the first patterned metal layer; and
forming a second patterned metal layer on the IMD layer,
wherein at least one portion of the first and second patterned metal layers overpass the region for PWs for high-voltage interconnection.
8. The method according to claim 1 , further comprising forming a first N-doped buried layer (NBL) adjacent to the first HVNW region and under the source and bulk PW.
9. The method according to claim 8 , further comprising forming a second N-doped buried layer (NBL) adjacent to the second HVNW region in the high-side operation region.
10. The method according to claim 9 , further comprising:
a third N-doped buried layer (NBL) disposed between the drain and the region for PWs.
11. The method according to claim 1 , wherein the n-type implant layer and P-Top layer beneath are formed as plural split blocks within the first HVNW region.