IP Library Granted Patent US 8,980,744
Granted Patent B2
US 8,980,744 · App. 13/675,852 · Granted Mar 17, 2015

Inexpensive electrode materials to facilitate rutile phase titanium oxide

Inventors: Hanhong Chen (Milpitas, CA); Toshiyuki Hirota (Higashihiroshima, JP); Pragati Kumar (Santa Clara, CA); Xiangxin Rui (Campbell, CA); Sunil Shanker (Santa Clara, CA)
Assignees: Intermolecular, Inc.; Elpida Memory, Inc.
H01L28/60H01L28/40C23C16/405H01L27/10852
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Quick Facts
Patent No.
US 8,980,744
App. No.
13/675,852
Granted
Mar 17, 2015
Kind
B2
Abstract

This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO 2 ) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Claims (40)

1. A method of fabricating a bottom electrode layer for use with a metal-insulator-metal assembly, the method comprising:

preparing a substrate,

wherein the preparing comprises an ozone scrubbing process, and

wherein a surface roughness of the substrate increases during the ozone scrubbing process;

fabricating a conductive layer on the substrate,

wherein the conductive layer comprises a nitride;

depositing an interface layer over the conductive laver,

wherein a thickness of the interface layer is less than a thickness of the conductive layer, and

wherein the interface layer comprises a conductive material oxide in a crystalline form; and

depositing a dielectric layer on the interface layer,

wherein the dielectric layer comprises titanium oxide having a rutile phase, and

wherein a lattice structure of a top surface of the interface layer is compatible with the rutile phase of titanium oxide of the dielectric layer.

2. A method as in claim 1 wherein the substrate comprises silicon.

3. A method as in claim 1 wherein fabricating the interface layer comprises chemical vapor deposition or atomic layer deposition.

4. A method as in claim 3 wherein the interface layer comprises MoO 2 .

5. A method as in claim 4 further comprising performing rapid thermal nitridazationof the interface layer thereby crystallizing the MoO 2 layer.

6. A method as in claim 1 wherein fabricating the interface layer comprises fabricating a non-conductive layer and treating the non-conductive layer to convert the non-conductive layer into the conductive metal oxide.

7. A method as in claim 6 wherein the non-conductive layer comprises MoO 3 and wherein the treatment of the non-conductive layer comprises a reducing anneal.

8. A method as in claim 6 wherein the non-conductive layer comprises a metal nitride and wherein the treatment of the non-conductive layer comprises oxidation.

9. A method as in claim 8 wherein the metal nitride comprises a molybdenum nitride.

10. A method of fabricating a bottom electrode layer for use with a metal-insulator-metal assembly, the method comprising:

preparing a substrate; and

fabricating a conductive layer on the substrate,

wherein the conductive layer comprises a nitride;

fabricating an interface layer on the conductive layer,

wherein a thickness of the interface layer is less than a thickness of the conductive layer, and

wherein the interface layer comprises a conductive material oxide in a crystalline form; and

fabricating a dielectric layer on the interface layer,

wherein the dielectric layer comprises titanium oxide having a rutile phase, and

wherein a lattice structure of the top surface of the interface layer is compatible with the rutile phase of titanium oxide of the dielectric layer.

11. A method as in claim 10 wherein the substrate comprises silicon.

12. A method as in claim 11 wherein preparing the substrate comprises an ozone scrubbing process.

13. A method as in claim 10 wherein fabricating the interface layer on comprises chemical vapor deposition or atomic layer deposition.

14. A method as in claim 13 wherein the interface layer comprises MoO 2 .

15. A method as in claim 14 further comprising performing rapid thermal nitridazation of the interface layer thereby crystallizing MoO 2 of the interface layer.

16. A method as in claim 10 wherein fabricating the interface layer comprises fabricating a non-conductive layer and treating the non-conductive layer to convert the non-conductive layer into the conductive metal oxide.

17. A method as in claim 16 wherein the non-conductive layer comprises MoO 3 and wherein the treatment of the non-conductive layer comprises a reducing anneal.

18. A method as in claim 16 wherein the non-conductive layer comprises a metal nitride and wherein the treatment of the non-conductive layer comprises oxidation.

19. A method as in claim 18 wherein the metal nitride comprises a molybdenum nitride.

20. A method as in claim 10 further comprises in-situ modification of the interface layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2014
From: INTERMOLECULAR, INC.
To: INTERMOLECULAR, INC.; ELPIDA MEMORY, INC.
Reel/Frame 032084/0787 →
Continuity (2)
Continuation 12708872 · Feb 19, 2010
Related Publication 20130072015A1 · Mar 21, 2013