High voltage three-dimensional devices having dielectric liners
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
1. A semiconductor structure, comprising:
a first fin active region and a second fin active region disposed above a substrate;
a first gate structure disposed above a top surface of, and along sidewalls of, the first fin active region, the first gate structure comprising a first gate dielectric, a first gate electrode, and first dielectric spacers, wherein the first gate dielectric comprises a first dielectric layer disposed on the first fin active region and along sidewalls of the first dielectric spacers and a second, different, dielectric layer disposed on the first dielectric layer and along the sidewalls of the first dielectric spacers; and
a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region, the second gate structure comprising a second gate dielectric, a second gate electrode, and second dielectric spacers, wherein the second gate dielectric comprises the second dielectric layer disposed on the second fin active region and along sidewalls of the second dielectric spacers.
2. The semiconductor structure of claim 1 , wherein the first fin active region and the second fin active region are disposed directly on the substrate.
3. The semiconductor structure of claim 2 , wherein the substrate is a bulk single crystalline silicon substrate, and the first fin active region and the second fin active region comprise single crystalline silicon.
4. The semiconductor structure of claim 1 , wherein the first dielectric layer comprises silicon oxide, and the second dielectric layer comprises a high-k material.
5. The semiconductor structure of claim 1 , wherein the second fin active region, but not the first fin active region, comprises a thin layer of thermal oxide at a top surface of the fin active region.
6. The semiconductor structure of claim 1 , further comprising:
a first pair of contacts disposed directly adjacent to the first dielectric spacers; and
a second pair of contacts disposed directly adjacent to the second dielectric spacers.
7. The semiconductor structure of claim 1 , wherein the first and second gate electrodes are metal gate electrodes.
8. The semiconductor structure of claim 1 , further comprising:
a high voltage device comprising the first gate structure; and
a low voltage device comprising the second gate structure.
9. A semiconductor structure, comprising:
a first plurality of fin active regions and a second plurality of fin active regions disposed above a substrate;
a high voltage device comprising a first gate dielectric and a first gate electrode and first dielectric spacers, wherein the first gate dielectric comprises a first dielectric layer disposed on the first plurality of fin active regions and along sidewalls of the first dielectric spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along the sidewalls of the first dielectric spacers; and
a low voltage device comprising a second gate dielectric and a second gate electrode and second dielectric spacers, wherein the second gate dielectric comprises the second dielectric layer disposed on the second plurality of fin active regions and along sidewalls of the second dielectric spacers.
10. The semiconductor structure of claim 9 , wherein the first plurality of fin active regions and the second plurality of fin active regions are disposed directly on the substrate.
11. The semiconductor structure of claim 10 , wherein the substrate is a bulk single crystalline silicon substrate, and the first plurality of fin active regions and the second plurality of fin active regions comprise single crystalline silicon.
12. The semiconductor structure of claim 9 , wherein the first dielectric layer comprises silicon oxide, and the second dielectric layer comprises a high-k material.
13. The semiconductor structure of claim 9 , wherein the second plurality of fin active regions, but not the first plurality of fin active regions, comprises a thin layer of thermal oxide at a top surface of the plurality of fin active regions.
14. The semiconductor structure of claim 9 , further comprising:
a first pair of contacts disposed directly adjacent to the first dielectric spacers; and
a second pair of contacts disposed directly adjacent to the second dielectric spacers.
15. The semiconductor structure of claim 9 , wherein the first and second gate electrodes are metal gate electrodes.