IP Library › Granted Patent US 8,982,604

Granted Patent B2

US 8,982,604 · App. 13/746,625 · Granted Mar 17, 2015

Resistive memory device and memory apparatus and data processing system having the same

Inventors: Keun Lee (Gyeonggi-do, KR); Se Hun Kang (Gyeonggi-do, KR); Ja Chun Ku (Gyeonggi-do, KR); Kwon Hong (Gyeonggi-do, KR)

Assignee: SK Hynix Inc.

H01L45/1253 G11C13/0002 H01L45/06 H01L45/1226 H01L45/1233 H01L45/1246 H01L45/126 H01L45/143 H01L45/144 H01L45/148 G11C13/0004

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Quick Facts

Patent No.: US 8,982,604
App. No.: 13/746,625
Granted: Mar 17, 2015
Kind: B2

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Abstract

A resistive memory device operable with low power consumption and a memory apparatus and data processing system including the same are provided. The resistive memory includes a chalcogenide compound containing 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te).

Claims (101)

1. A memory device, comprising:

a lower electrode to be electrically connected an access device;

a data storage node, including a variable resistive material layer, to be heated by the lower electrode, the variable resistive material layer comprising a chalcogenide compound comprising 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te); and

an upper electrode connected to the data storage node,

wherein the chalcogenide compound comprises a material selected from the group consisting of (i) a tin-antimony-selenium (Sn—Sb—Se) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %, (ii) a germanium-antimony-selenium (Ge—Sb—Se) compound, wherein an amount of the Ge is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %, (iii) a tin-antimony-tellurium (Sn—Sb—Te) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %, and (iv) a silicon-antimony-tellurium (Si—Sb—Te) compound, wherein an amount of the Si is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

2. A resistive memory device, comprising:

a data storage node including variable resistive material layers alternately stacked with insulating layers, wherein one of the variable resistive material layers is formed of a chalcogenide compound comprising 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te);

a lower electrode surrounding the insulating layers and the variable resistive material layers at one sidewall of the data storage node; and

an upper electrode surrounding the insulating layers and the variable resistive material layers at another sidewall of the data storage node.

3. The resistive memory device of claim 2 , wherein the chalcogenide compound further comprises:

one of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (in), in combination with the Se or the Te.

4. The resistive memory device of claim 2 , wherein the chalcogenide compound further comprises:

at least two of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (In), in combination with the Se or the Te.

5. The resistive memory device of claim 2 , wherein the chalcogenide compound further comprises:

a tin-antimony-selenium (Sn—Sb—Se) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

6. The resistive memory device of claim 4 , wherein the chalcogenide compound further comprises:

a germanium-antimony-selenium (Ge—Sb—Se) compound, wherein an amount of the Ge is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

7. The resistive memory device of claim 2 , wherein the chalcogenide compound further comprises:

a tin-antimony-tellurium (Sn—Sb—Te) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

8. The resistive memory device of claim 2 , wherein the chalcogenide compound further comprises:

a silicon-antimony-tellurium (Si—Sb—Te) compound, wherein an amount of the Si is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

9. The resistive memory device of claim 2 , wherein the variable resistive material layers are formed of the same material or of different materials.

10. A memory device, comprising:

a lower electrode electrically connected to the variable resistive material layers at one sidewall of the data storage node; and

an upper electrode formed to surrounding the insulating layers and the variable resistive material layers in another sidewall of the data storage node.

11. The memory device of claim 10 , wherein the chalcogenide compound further comprises:

one of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (in), in combination with the Se or the Te.

12. The memory device of claim 10 , wherein the chalcogenide compound further comprises:

at least two of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (In), in combination with the Se or the Te.

13. The memory device of claim 10 , wherein the chalcogenide compound further comprises:

a tin-antimony-selenium (Sn—Sb—Se) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

14. The memory device of claim 10 , wherein the chalcogenide compound further comprises:

a germanium-antimony-selenium (Ge—Sb—Se) compound, wherein an amount of the Ge is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

15. The memory device of claim 10 , wherein the chalcogenide compound further comprises:

a tin-antimony-tellurium (Sn—Sb—Te) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

16. The memory device of claim 10 , wherein the chalcogenide compound further comprises:

a silicon-antimony-tellurium (Si—Sb—Te) compound, wherein an amount of the Si is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

17. The memory device of claim 10 , wherein the variable resistive material layers are formed of the same material or of different materials.

18. The memory device of claim 10 , wherein the lower electrode is electrically connected to the variable resistive material layers and the variable resistive material layers are formed of the same material or of different materials.

19. A resistive memory device, comprising:

a first lower electrode;

a second lower electrode formed on the first lower electrode, the second lower electrode including a via hole exposing the lower electrode;

a first variable resistive material layer buried in the via hole;

a second variable resistive material layer formed on the second lower electrode and on the first variable resistive material layer; and

an upper electrode formed on the second variable resistive material layer,

wherein the first variable resistive material layer or the second variable resistive material layer is formed of a chalcogenide compound comprising 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te).

20. The resistive memory device of claim 19 , wherein the chalcogenide compound further comprises:

one of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (in), in combination with the Se or the Te.

21. The resistive memory device of claim 19 , wherein the chalcogenide compound further comprises:

at least two of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (In), in combination with the Se or the Te.

22. The resistive memory device of claim 19 , wherein the chalcogenide compound further comprises:

a tin-antimony-selenium (Sn—Sb—Se) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

23. The resistive memory device of claim 19 , wherein the chalcogenide compound further comprises:

a germanium-antimony-selenium (Ge—Sb—Se) compound, wherein an amount of the Ge is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

24. The resistive memory device of claim 19 , wherein the chalcogenide compound further comprises:

a tin-antimony-tellurium (Sn—Sb—Te) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

25. The resistive memory device of claim 19 , wherein the chalcogenide compound further comprises:

a silicon-antimony-tellurium (Si—Sb—Te) compound, wherein an amount of the Si is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

26. The resistive memory device of claim 19 , wherein the first variable resistive material layer and the second variable resistive material layer are formed of the same material or of different materials.

27. The resistive memory device of claim 19 , wherein the first lower electrode and the second lower electrode are formed of the same material or of different materials.

28. A resistive memory device, comprising:

a first lower electrode;

a second lower electrode formed on a periphery of the first lower electrode;

a first variable resistive material layer buried in an inner circumference of the second lower electrode;

a second variable resistive material layer formed on the second lower electrode and the first variable resistive material layer to be electrically connected to the second lower electrode and the first variable resistive material layer; and

an upper electrode formed on the second variable resistive material layer,

wherein the first variable resistive material layer or the second variable resistive material layer is foil red of a chalcogenide compound comprising 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te).

29. The resistive memory device of claim 28 , wherein the chalcogenide compound further comprises:

one of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (in), in combination with the Se or the Te.

30. The resistive memory device of claim 28 , wherein the chalcogenide compound further comprises:

at least two of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), and indium (In), in combination with the Se or the Te.

31. The resistive memory device of claim 28 , wherein the chalcogenide compound further comprises:

a tin-antimony-selenium (Sn—Sb—Se) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

32. The resistive memory device of claim 28 , wherein the chalcogenide compound further comprises:

a germanium-antimony-selenium (Ge—Sb—Se) compound, wherein an amount of the Ge is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.

33. The resistive memory device of claim 28 , wherein the chalcogenide compound further comprises:

a tin-antimony-tellurium (Sn—Sb—Te) compound, wherein an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

34. The resistive memory device of claim 28 , wherein the chalcogenide compound further comprises:

a silicon-antimony-tellurium (Si—Sb—Te) compound, wherein an amount of the Si is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Te is 10 to 60 wt %.

35. The resistive memory device of claim 28 , wherein the first variable resistive material layer and the second variable resistive material layer are formed of the same material or of different materials.

36. The resistive memory device of claim 28 , wherein the first lower electrode and the second lower electrode are formed of the same material or of different materials.

37. A memory apparatus, comprising:

a memory cell array, including a plurality of memory cells, connected between a word line and a bit line; and

a controller, connected to the memory cell array, to control data reading and writing for the memory cell array,

wherein each of the plurality of memory cells includes a resistive memory device including a variable resistive material layer formed of a chalcogenide compound comprising 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te),

38. A data processing system, comprising:

a resistive memory apparatus including a memory cell array in which resistive memory devices are connected between bit lines and word lines;

a memory controller to access the resistive memory apparatus in response to request of a host; and

a controller to control an operation of the memory cell array,

wherein each of the resistive memory devices is a resistive memory device including a variable resistive material layer formed of a chalcogenide compound comprising 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te),

39. A data processing system, comprising:

a processor;

a memory storing data for use by the processor;

a resistive memory apparatus connected to the processor, wherein the resistive memory apparatus includes a memory cell array in which resistive memory devices are connected between bit lines and word lines;

a user interface to input data and output data between the processor and a user; and

a controller to control an operation of the memory cell array,

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2013

From: LEE, KEUN; KANG, SE HUN; KU, JA CHUN; HONG, KWON

To: SK HYNIX INC.

Reel/Frame 029669/0292 →

Priority Claims (1)

KR 10-2012-0065800 · Jun 19, 2012 · national

Continuity (1)

Related Publication 20130336042A1 · Dec 19, 2013