Receiver circuit and semiconductor integrated circuit

1. A receiver circuit comprising:

a sampling circuit which detects an amplitude level of an input data signal at a sampling timing indicated by a sampling clock;

a first comparison circuit which compares a first amplitude level and a second amplitude level detected by the sampling circuit at a first sampling timing and a second sampling timing, respectively, with a determined threshold;

an interpolation circuit which calculates an intermediate level that approximates to an amplitude level of the input data signal corresponding to an intermediate point between the first sampling timing and the second sampling timing by an interpolation process based on the first amplitude level and the second amplitude level;

a second comparison circuit which compares the intermediate level with the determined threshold; and

a phase deviation detection circuit which detects a deviation of phase between the sampling clock and the input data signal on the basis of results of comparisons made by the first comparison circuit and the second comparison circuit.

2. The receiver circuit according to claim 1 , wherein when a combination of a first bit value and a second bit value corresponding to the first amplitude level and the second amplitude level, respectively, and a third bit value and a fourth bit value corresponding to a third amplitude level and a fourth amplitude level detected by the sampling circuit at a third sampling timing and a fourth sampling timing, respectively, different from the first sampling timing and the second sampling timing does not form a determined pattern, the phase deviation detection circuit detects the deviation of phase.

3. The receiver circuit according to claim 2 , wherein the determined pattern is a pattern in which bit value inversion is repeated periodically.

4. The receiver circuit according to claim 2 , wherein:

when a slew rate of the input data signal is greater than a determined pattern decision threshold, the phase deviation detection circuit considers as the determined pattern a first pattern obtained by combining the first through fourth bit values; and

when the slew rate of the input data signal is smaller than the determined pattern decision threshold, the phase deviation detection circuit considers as the determined pattern a second pattern obtained by combining the first bit value and the second bit value or a third pattern obtained by combining the first bit value, the second bit value, and the third bit value or the fourth bit value.

5. The receiver circuit according to claim 2 , wherein:

when an interval between the first sampling timing and the second sampling timing is shorter than a determined pattern decision threshold, the phase deviation detection circuit considers as the determined pattern a first pattern obtained by combining the first through fourth bit values; and

when the interval between the first sampling timing and the second sampling timing is longer than the determined pattern decision threshold, the phase deviation detection circuit considers as the determined pattern a second pattern obtained by combining the first bit value and the second bit value or a third pattern obtained by combining the first bit value, the second bit value, and the third bit value or the fourth bit value.

6. The receiver circuit according to claim 4 , wherein:

the first comparison circuit is a decision feedback equalizer; and

the slew rate is calculated from an equalization coefficient of the decision feedback equalizer.

7. The receiver circuit according to claim 1 , wherein:

the interpolation circuit includes:

a first capacitance whose one end is connected to a first node whose potential corresponds to an amplitude level of the input data signal at the first sampling timing and whose other end is connected to a first output terminal;

a second capacitance whose one end is connected to the first node, whose other end is connected to a second output terminal, and whose capacitance value is half of a capacitance value of the first capacitance;

a third capacitance whose one end is connected to a second node whose potential corresponds to an amplitude level of the input data signal at the second sampling timing, whose other end is connected to the second output terminal, and whose capacitance value is half of the capacitance value of the first capacitance; and

a control circuit which exercises control so that the first node is kept at determined potential after reaching the potential corresponding to the amplitude level of the input data signal, and which exercises control so that the second node is kept at the determined potential after reaching the potential corresponding to the amplitude level of the input data signal,

wherein:

when control is exercised so that the first node is kept at the determined potential, potential outputted from the first output terminal is outputted as the first amplitude level; and

after control is exercised so that the second node is kept at the determined potential, potential outputted from the second output terminal is outputted as the intermediate level.

8. A semiconductor integrated circuit including a receiver circuit which can correct a deviation of phase between an input data signal and a sampling clock and a logic circuit which operates by the use of data and a clock outputted from the receiver circuit, the receiver circuit comprising:

a sampling circuit which detects an amplitude level of the input data signal at a sampling timing indicated by the sampling clock;

a first comparison circuit which compares a first amplitude level and a second amplitude level detected by the sampling circuit at a first sampling timing and a second sampling timing, respectively, with a determined threshold;

an interpolation circuit which calculates an intermediate level that approximates to an amplitude level of the input data signal corresponding to an intermediate point between the first sampling timing and the second sampling timing by an interpolation process based on the first amplitude level and the second amplitude level;

a second comparison circuit which compares the intermediate level with the determined threshold;

a phase deviation detection circuit which detects the deviation of phase between the sampling clock and the input data signal on the basis of results of comparisons made by the first comparison circuit and the second comparison circuit; and

a phase adjustment circuit which adjusts a phase of the sampling clock to correct the deviation of phase detected by the phase deviation detection circuit,

wherein:

the result of the comparison made by the first comparison circuit is inputted as the data to the logic circuit; and

the sampling clock whose phase is adjusted by the phase adjustment circuit is inputted as the clock to the logic circuit.