Method of using a buffer within an indexing accelerator during periods of inactivity

1. A method of using a buffer within an indexing accelerator during periods of inactivity, comprising:

flushing indexing specific data located in the buffer;

disabling a controller within the indexing accelerator;

handing control of the buffer over to a higher level cache; and

selecting one of a number of operation modes of the buffer.

2. The method of claim 1 , in which the operation modes comprise:

a victim cache mode;

a miss buffer mode;

a stream buffer mode; or

an optimization buffer mode.

3. The method of claim 1 , further comprising receiving an operation request from a processing core to re-enable indexing operations on the indexing accelerator.

4. The method of claim 3 , further comprising:

invalidating all buffer data within the buffer; and

re-enabling the controller within the indexing accelerator.

5. The method of claim 4 , further comprising:

disabling a number of cache ways within the higher level cache after selecting one of a number of operation modes of the buffer; and

re-enabling the number of cache ways within the higher level cache after re-enabling the controller within the indexing accelerator.

6. The method of claim 1 , in which the operation modes comprises using the buffer as a scratch pad memory.

7. An indexing accelerator, comprising:

a controller; and

a buffer communicatively coupled to the controller;

in which, during periods of inactivity, the controller is disabled and a buffer operating mode among a number of operating modes is chosen under which the buffer will be used.

8. The indexing accelerator of claim 7 , in which the operation modes comprise:

a victim cache mode;

a miss buffer mode;

a stream buffer mode; or

an optimization buffer mode.

9. The indexing accelerator of claim 7 , in which indexing specific data located in the buffer is flushed prior to the controller being disabled.

10. The indexing accelerator of claim 7 , in which control of the buffer is handed over to a higher level cache for use by that cache under one of the number of operation modes.

11. The indexing accelerator of claim 7 , in which operation of the indexing accelerator as an indexing accelerator is accomplished by:

receiving an operation request from a processing core to re-enable indexing operations on the indexing accelerator;

invalidating all buffer data within the buffer; and

re-enabling the controller within the indexing accelerator.

12. The indexing accelerator of claim 11 , in which:

a number of cache ways within the higher level cache are disabled after choosing one of a number of operation modes of the buffer; and

the number of cache ways within the higher level cache are re-enabled after re-enabling the controller within the indexing accelerator.

13. A computer program product for using a buffer within an indexing accelerator during periods of inactivity, the computer program product comprising:

a computer readable storage medium comprising computer usable program code embodied therewith to, when executed by a processor:

flush indexing specific data located in the buffer;

disable a controller within the indexing accelerator;

hand over control of the buffer to a higher level cache; and,

select one of a number of operation modes of the buffer.

14. The computer program product of claim 13 , in which the operation modes comprise:

a victim cache mode;

a miss buffer mode;

a stream buffer mode; or

an optimization buffer mode.

15. The computer program product of claim 13 , further comprising computer usable program code to, when executed by a processor:

receive an operation request from a processing core to re-enable indexing operations on the indexing accelerator;

invalidate all buffer data within the buffer; and

re-enable the controller within the indexing accelerator.