Method and apparatus for automatic relative placement generation for clock trees
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
1. A method of circuit design with a computer system, comprising:
generating with the computer system a placed, routed, and optimized circuit design, including:
performing an initial placement for a netlist of the circuit design according to a first set of rules;
creating a second set of rules for clock network flip-flops in the netlist of the circuit design based on a result of the initial placement, wherein the second set of rules result in bringing the clock network flip-flops closer together, and
completing placement, routing, and optimization of the netlist of the circuit design according to the first set and the second set of rules.
2. The method of claim 1 , further including:
the rules for the clock network flip-flops in the netlist of the circuit design relate to at least one clock sink in the netlist.
3. The method of claim 1 , further including:
after the initial placement, automatically grouping the clock network flip-flops into a plurality of flip-flop groups.
4. The method of claim 1 , further including:
after the initial placement, automatically grouping the clock network flip-flops into a plurality of flip-flop groups,
wherein the rules automatically created for the clock network flip-flops are based on the plurality of flip-flop groups.
5. The method of claim 1 , further including:
after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups.
6. The method of claim 1 , further including:
after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups, without creating clock network buffer circuitry.
7. The method of claim 1 , further including:
after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups,
wherein the rules automatically created for the clock network flip-flops are based on the plurality of flip-flop groups from the clock tree clustering.
8. The method of claim 1 , further including:
after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups; and
during placement of the circuit design, automatically creating clock network buffer circuitry for the plurality of flip-flop groups.
9. The method of claim 1 , wherein the clock network flip-flops are leaf nodes of a clock tree of the circuit design.
10. The method of claim 1 , further including:
during placement of the circuit design, automatically adding clock network buffer circuitry matched to the grouped clock network flip-flops in the circuit design.
11. The method of claim 1 , wherein the rules obey clock tree constraints specified for the circuit design.
12. A tangible non-transitory computer readable medium with computer readable instructions executable by a computer system, comprising:
instructions generating with the computer system a placed, routed, and optimized circuit design, including:
instructions performing an initial placement for a netlist of the circuit design according to a first set of rules;
instructions creating a second set of rules for clock network flip-flops in the netlist of the circuit design based on a result of the initial placement, wherein the second set of rules result in bringing the clock network flip-flops closer together, and
instructions completing placement, routing, and optimization of the netlist of the circuit design according to the first set and the second set of rules.
13. The computer readable medium of claim 12 ,
wherein the rules for the clock network flip-flops in the netlist of the circuit design relate to at least one clock sink in the netlist.
14. The computer readable medium of claim 12 , further including:
instructions, after the initial placement, automatically grouping the clock network flip-flops into a plurality of flip-flop groups.
15. The computer readable medium of claim 12 , further including:
instructions, after the initial placement, automatically grouping the clock network flip-flops into a plurality of flip-flop groups,
wherein the rules automatically created for the clock network flip-flops are based on the plurality of flip-flop groups.
16. The computer readable medium of claim 12 , further including:
instructions, after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups.
17. The computer readable medium of claim 12 , further including:
instructions, after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups, without creating clock network buffer circuitry.
18. The computer readable medium of claim 12 , further including:
instructions, after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups,
wherein the rules automatically created for the clock network flip-flops are based on the plurality of flip-flop groups from the clock tree clustering.
19. The computer readable medium of claim 12 , further including:
instructions, after the initial placement, performing clock tree clustering that automatically groups the clock network flip-flops into a plurality of flip-flop groups; and
during placement of the circuit design, automatically creating clock network buffer circuitry for the plurality of flip-flop groups.
20. The computer readable medium of claim 12 , wherein the clock network flip-flops are leaf nodes of a clock tree of the circuit design.
21. The computer readable medium of claim 12 , further including:
instructions, during placement of the circuit design, automatically adding clock network buffer circuitry matched to the grouped clock network flip-flops in the circuit design.
22. The computer readable medium of claim 12 , wherein the rules obey clock tree constraints specified for the circuit design.
23. A data processing system adapted to process a computer implemented representation of a circuit design, comprising:
a data processor and memory coupled to the data processor, the memory storing instructions executable by the data processor, the instructions including:
instructions generating with the computer system a placed, routed, and optimized circuit design, including:
instructions performing an initial placement for a netlist of the circuit design according to a first set of rules;
instructions creating a second set of rules for clock network flip-flops in the netlist of the circuit design based on a result of the initial placement, wherein the second set of rules result in bringing the clock network flip-flops closer together, and
instructions completing placement, routing, and optimization of the netlist of the circuit design according to the first set and the second set of rules.
24. A circuit, comprising:
a circuit following a placed, routed, and optimized circuit design, wherein the placed, routed, and optimized circuit design is created by:
performing an initial placement for a netlist of the circuit design according to a first set of rules;
creating a second set of rules for clock network flip-flops in the netlist of the circuit design based on a result of the initial placement, wherein the second set of rules result in bringing the clock network flip-flops closer together, and
completing placement, routing, and optimization of the netlist of the circuit design according to the first set and the second set of rules.
25. The method of claim 1 , wherein the second set of rules specify positioning of the clock network flip-flops relative to each other.
26. The method of claim 1 , wherein the first set and the second set of rules specify positioning of the clock network flip-flops relative to each other and relative to other circuit elements in the circuit design.
27. The method of claim 3 , wherein said automatically grouping the clock network flip-flops into the plurality of flip-flop groups, precedes clock tree synthesis of the circuit design.