Method of fabricating fin-field effect transistors (finfets) having different fin widths

1. A method of fabricating an integrated circuit device, the method comprising:

forming fin-shaped transistor channel regions having respective widths that are the same and protruding from coplanar first and second regions of a substrate surface; and

after forming the fin-shaped transistor channel regions having the respective widths that are the same, selectively altering the respective widths of ones of the fin-shaped transistor channel regions protruding from the first region while maintaining the respective widths of ones of the fin-shaped transistor channel regions protruding from the second region,

wherein, after selectively altering the respective widths, the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region are different than the respective widths of the ones of the fin-shaped transistor channel regions protruding from the second region.

2. The method of claim 1 , wherein, after forming the fin-shaped transistor channel regions having the respective widths that are the same, selectively altering comprises one of etching sidewalls of the ones of the fin-shaped transistor channel regions protruding from the first region or growing a semiconductor layer of a same conductivity type on the sidewalls such that, after selectively altering the respective widths, the ones of the fin-shaped transistor channel regions protruding from the second region define different transistor threshold voltages than the ones of the fin-shaped transistor channel regions protruding from the first region.

3. The method of claim 2 , wherein, after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region, respective heights of the ones of the fin-shaped transistor channel regions protruding from the first and second regions are substantially similar.

4. The method of claim 2 , wherein, after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region, the first and second regions of the substrate surface are non-coplanar.

5. The method of claim 2 , further comprising:

doping the substrate prior to selectively altering the respective widths of the ones of the first fin-shaped transistor channel regions,

wherein, after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region, the ones of the fin-shaped transistor channel regions protruding from the first region have different doping concentrations or doping amounts than the ones of the fin-shaped transistor channel regions protruding from the second region.

6. A method of forming field effect transistors, comprising:

forming fin portions having widths that are the same on first and second regions of a substrate, each of the fin portions protruding from the substrate;

after forming the fin portions, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region; and

after forming the first mask pattern, changing the widths of the fin portions provided on the first region without changing the widths of the fin portions provided on the second region such that the fin portions provided on the first region define different transistor threshold voltages than the fin portions provided on the second region.

7. The method of claim 6 , wherein changing the widths of the fin portions comprises growing a semiconductor layer of a same conductivity type on the fin portions.

8. The method of claim 6 , further comprising forming device isolation layers on lower sidewalls of the fin portions such that upper sidewalls of the fin portions are free of the device isolation layers,

wherein the semiconductor layer is formed before forming the device isolation layers.

9. The method of claim 8 , wherein the forming of the fin portions comprises:

forming second mask patterns on the substrate; and

etching the substrate using the second mask patterns as an etch mask,

wherein the semiconductor layer is formed on sidewalls of the fin portions and on a top surface of the substrate exposed by the first and second mask patterns.

10. The method of claim 7 , further comprising forming device isolation layers on lower sidewalls of the fin portions such that upper sidewalls of the fin portions are free of the device isolation layers,

wherein the first mask pattern and the semiconductor layer are formed after forming the device isolation layers.

11. The method of claim 10 , wherein the semiconductor layer is formed on upper sidewalls and top surfaces of the fin portions exposed by the device isolation layers and the first mask pattern.

12. The method of claim 7 , wherein the semiconductor layer comprises a material having a different lattice constant and/or bandgap from the fin portions.

13. The method of claim 6 , wherein changing the widths of the fin portions comprises etching sidewalls of the fin portions provided on the first region, wherein the fin portions comprise part of the substrate.

14. The method of claim 13 , further comprising forming device isolation layers on lower sidewalls of the fin portions such that upper sidewalls of the fin portions are free of the device isolation layers,

wherein the device isolation layers are formed after etching the fin portions.

15. The method of claim 14 , wherein the forming the fin portions comprises:

forming second mask patterns on the substrate; and

etching the substrate using the second mask patterns as an etch mask,

wherein etching the fin portions comprises etching sidewalls of the fin portions and a top surface of the substrate exposed by the first and second mask patterns.

16. The method of claim 13 , further comprising forming device isolation layers on lower sidewalls of the fin portions,

wherein the device isolation layers are formed before etching the fin portions, and wherein etching the fin portions comprises etching top surfaces and upper sidewalls of the fin portions exposed by the first mask pattern and the device isolation layers.

17. The method of claim 6 , wherein forming the fin portions comprises:

forming second mask patterns on the substrate; and

etching the substrate using the second mask patterns as an etch mask,

wherein forming the second mask patterns comprises:

forming third mask patterns on the substrate;

performing a spacer-forming process to farm the second mask patterns on sidewalls of the third mask patterns; and

removing the third mask patterns.

18. The method of claim 17 , wherein respective widths of the second mask patterns are substantially equal.

19. A method of fabricating an integrated circuit device, the method comprising:

forming fin-shaped transistor channel regions having respective widths that are the same protruding from coplanar first and second regions of a substrate surface; and

after forming the fin-shaped transistor channel regions having the respective widths that are the same, selectively altering the respective widths of ones of the fin-shaped transistor channel regions protruding from the first region while maintaining the respective widths of ones of the fin-shaped transistor channel regions protruding from the second region by etching sidewalls of the ones of the fin-shaped transistor channel regions protruding from the first region or growing a semiconductor layer of a same conductivity type on the sidewalls such that the ones of the fin-shaped transistor channel regions protruding from the first region have different doping concentrations or doping amounts that define different transistor threshold voltages than the ones of the fin-shaped transistor channel regions protruding from the second region,

wherein, after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region, the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region are different than the respective widths of the ones of the fin-shaped transistor channel regions protruding from the second region, and respective heights of the ones of the fin-shaped transistor channel regions protruding from the first and second regions are substantially similar.