Method and system for advance high performance bus synchronizer
Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.
1. A method for transferring data from one clock domain within an advanced high performance bus synchronizer to another domain within the synchronizer while preserving burst operations, comprising:
determining system clock parameters within the synchronizer;
analyzing a first clock signal associated with a first clock domain based upon the system clock parameters;
analyzing a second clock signal associated with a second clock domain based upon the first clock signal and the system clock parameters;
switching an operational mode of the synchronizer based on a ratio of frequencies of the first and second clock signals, wherein the switching of the operational mode includes switching between a latency mode, a bandwidth mode, and a bypass mode, the bypass mode including bypassing a transfer of data between the first clock domain and the second clock domain and bypassing a transfer of data between the second clock domain and the first clock domain; and
providing a second clock domain enable signal to enable a rising edge of the second clock signal to transfer data between the first clock domain and the second clock domain and a first clock domain enable signal to enable a rising edge of the first clock signal to transfer data between the second clock domain and the first clock domain.
2. The method of claim 1 , wherein the analysis of the first clock signal includes locating the rising edge of the first clock signal.
3. The method of claim 2 , wherein the analysis of the second clock signal includes locating the rising edge of the second clock signal.
4. The method of claim 1 , wherein the first clock domain is a master clock domain; and
wherein the second clock domain is a slave clock domain.
5. An apparatus for transferring data from one clock domain within an advanced high performance bus synchronizer to another domain within the synchronizer while preserving burst operations, comprising:
means for determining system clock parameters within the synchronizer;
means for analyzing a first clock signal associated with a first clock domain based upon the system clock parameters;
means for analyzing a second clock signal associated with a second clock domain based upon the first clock signal and the system clock parameters;
means for switching an operational mode of the synchronizer based on a ratio of frequencies of the first and second clock signals, wherein the means for switching is configured to switch between a latency mode, a bandwidth mode, and a bypass mode based on the ratio of frequencies, the bypass mode including bypassing a transfer of data between the first clock domain and the second clock domain and bypassing a transfer of data between the second clock domain and the first clock domain; and
means for providing a second clock domain enable signal to enable a rising edge of the second clock signal to transfer data between the first clock domain and the second clock domain and a first clock domain enable signal to enable a rising edge of the first clock signal to transfer data between the second clock domain and the first clock domain.
6. The apparatus of claim 5 , wherein an analysis of the first clock signal includes locating the rising edge of the first clock signal.
7. The apparatus of claim 6 , wherein the analysis of the second clock signal includes locating the rising edge of the second clock signal.
8. The apparatus of claim 5 , wherein the first clock domain is a master clock domain; and
wherein the second clock domain is a slave clock domain.
9. The method of claim 1 , wherein a falling edge of the second clock domain enable signal enables the transfer of the data between the first clock domain and the second clock domain, and wherein a falling edge of the first clock domain enable signal enables the transfer of the data between the second clock domain and the first clock domain.
10. The method of claim 1 , wherein a falling edge of the second clock domain enable signal enables a rising edge of the second clock signal to capture the data transferred between the first clock domain and the second clock domain from a rising edge of the first clock signal.
11. The method of claim 10 , wherein the falling edge of the second clock domain enable signal is aligned with the rising edge of the second clock signal that captures the data from the rising edge of the first clock signal.
12. The method of claim 1 , wherein a falling edge of the first clock domain enable signal enables a rising edge of the first clock signal to capture the data transferred between the second clock domain and the first clock domain from a rising edge of the second clock signal.
13. The method of claim 12 , wherein the falling edge of the first clock domain enable signal is aligned with the rising edge of the first clock signal that captures the data from the rising edge of the second clock signal.
14. The apparatus of claim 5 , wherein a falling edge of the second clock domain enable signal enables the transfer of the data between the first clock domain and the second clock domain, and wherein a falling edge of the first clock domain enable signal enables the transfer of the data between the second clock domain and the first clock domain.
15. The apparatus of claim 5 , wherein a falling edge of the second clock domain enable signal enables a rising edge of the second clock signal to capture the data transferred between the first clock domain and the second clock domain from a rising edge of the first clock signal.
16. The apparatus of claim 15 , wherein the falling edge of the second clock domain enable signal is aligned with the rising edge of the second clock signal that captures the data from the rising edge of the first clock signal.
17. The apparatus of claim 5 , wherein a falling edge of the first clock domain enable signal enables a rising edge of the first clock signal to capture the data transferred between the second clock domain and the first clock domain from a rising edge of the second clock signal.
18. The apparatus of claim 17 , wherein the falling edge of the first clock domain enable signal is aligned with the rising edge of the first clock signal that captures the data from the rising edge of the second clock signal.
19. An apparatus for transferring data from one clock domain within an advanced high performance bus synchronizer to another domain within the synchronizer while preserving burst operations, comprising:
means for determining system clock parameters within the synchronizer;
means for analyzing a first clock signal associated with a first clock domain based upon the system clock parameters;
means for analyzing a second clock signal associated with a second clock domain based upon the first clock signal and the system clock parameters; and
means for providing a second clock domain enable signal to enable a rising edge of the second clock signal to transfer data between the first clock domain and the second clock domain, and a first clock domain enable signal to enable a rising edge of the first clock signal to transfer data between the second clock domain and the first clock domain, the means for providing being configured to operate in a bypass mode, a bandwidth mode, and a latency mode, wherein the bypass mode includes bypassing the transfer of the data between the first clock domain and the second clock domain and bypassing the transfer of the data between the second clock domain and the first clock domain; wherein the bandwidth mode includes maximizing bandwidth of the synchronizer; and wherein the latency mode includes minimizing latency in the synchronizer.