Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards
Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.
1. An integrated circuit (IC) chip comprising a plurality of pins disposed on a common plane of the IC chip, the pins are grouped into a plurality of concentric rings, wherein the pins are assigned to a plurality of signal nets, and wherein each of the signal nets is assigned to a respective one of the plurality of concentric rings according to at least one of: (i) a plurality of different signal speeds associated with the signal nets and (ii) differing amounts of circuitry associated with the signal nets.
2. The IC of claim 1 , wherein a portion of the pins are assigned to ground and arranged in L-shaped patterns.
3. The IC of claim 1 , wherein a portion of the pins are assigned to power nets and grouped at or near an innermost ring to form a power core.
4. The IC of claim 3 , wherein the power core is shaped as a square, circle, oval, ellipse, rectangle, diamond, or cross.
5. The IC of claim 1 , wherein the plurality of pins is divided into quadrants and a portion of the pins is assigned to signal nets grouped into the quadrants based on a general direction in which each of the signal nets will be routed away from the pins as viewed from a top surface of the IC that includes the plurality of pins.
6. An integrated circuit (IC) chip comprising a plurality of pins divided into a plurality of concentric rings, wherein the pins are assigned to signal nets grouped into the plurality of concentric rings according to at least one of signal speed and an amount of circuitry associated with a respective signal net, wherein the highest speed signal nets are assigned to pins within outermost rings and the signal speed of the signal nets generally decreases when moving from the outermost rings to innermost rings.
7. The IC of claim 6 , wherein a portion of the pins are assigned to ground and arranged in L-shaped patterns.
8. The IC of claim 6 , wherein a portion of the pins are assigned to power nets and grouped at or near an innermost ring to form a power core.
9. The IC of claim 8 , wherein the power core is shaped as a square, circle, oval, ellipse, rectangle, diamond, or cross.
10. The IC of claim 8 , wherein the plurality of pins is divided into quadrants and a portion of the pins are assigned to signal nets grouped into the quadrants based on a general direction in which each of the signal nets will be routed away from the pins as viewed from a top surface of the IC that includes the plurality of pins.
11. An integrated circuit (IC), comprising a plurality of pins divided into a plurality of concentric rings, wherein the pins are assigned to a plurality of signal nets grouped into the plurality of concentric rings according to at least one of signal speed and an amount of associated circuitry, wherein the highest speed signal nets are assigned to pins within outermost rings and the signal speed of the plurality of signal nets generally decreases when moving from the outermost rings to innermost rings,
wherein a portion of the pins are assigned to power nets of the plurality of signal nets and grouped at or near an innermost ring to form a power core,
wherein the plurality of concentric rings comprises an outermost ring, the innermost ring, and a middle ring between the outermost and innermost rings, wherein the pins in the innermost ring are assigned to the power nets, the pins in the middle ring are assigned to first signal nets of the plurality of signal nets with higher speed signals than the power nets, and the pins in the outermost ring are assigned to second signal nets of the plurality of signal nets with higher speed signals than the first signal nets.
12. An integrated circuit (IC) chip comprising a plurality of pins divided into a plurality of concentric rings, wherein the pins are assigned to signal nets grouped into the plurality of concentric rings according to at least one of signal speed and an amount of circuitry associated with a respective signal net, wherein the signal nets associated with the most circuitry are assigned to pins within innermost rings, and the amount of associated circuitry generally decreases when moving from the innermost rings to outermost rings.
13. The IC of claim 12 , wherein the IC is configured to couple to a top surface of a printed circuit board (PCB) via the pins, wherein the associated circuitry is mounted on the PCB and connected to the pins of the IC via the top surface.
14. The IC of claim 13 , wherein the associated circuitry is disposed on a bottom surface of the PCB.
15. The IC of claim 12 , wherein a portion of the pins are assigned to ground and arranged in L-shaped patterns.
16. The IC of claim 12 , wherein a portion of the pins are assigned to power nets and grouped at or near an innermost ring to form a power core.
17. The IC of claim 16 , wherein the power core is shaped as a square, circle, oval, ellipse, rectangle, diamond, or cross.
18. The IC of claim 12 , wherein the plurality of pins is divided into quadrants and a portion of the pins are assigned to signal nets grouped into the quadrants based on a general direction in which each of the signal nets will be routed away from the pins as viewed from a surface of the IC that includes the plurality of pins.
19. The IC of claim 12 , wherein the associated circuitry comprises at least one of a bypass capacitor or a termination resistor.