Chip stack with electrically insulating walls
View Patent ↗A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.
1. A method of forming a chip stack, comprising:
arraying solder pads along a plane of a major surface of a substrate, the solder pads each having an outer surface disposed outwardly from a conductor and above insulators and an inner surface recessed from the outer surface and disposed in contact with the conductor; and
forming walls of electrically insulating material between adjacent ones of the solder pads such that the walls extend from uppermost surfaces of the insulators and are displaced from each of the adjacent ones of the solder pads.
2. The method according to claim 1 , wherein the arraying of the solder pads comprises plating of solder pad material on the major surface.
3. The method according to claim 1 , wherein the forming of the walls comprises forming the walls as a continuous wall.
4. The method according to claim 1 , wherein the forming of the continuous wall comprises forming a hexagonal array.
5. A method of forming a chip stack, comprising:
forming a chip stack element to include a substrate having two major surfaces, solder pads arrayed along a plane of one of the major surfaces with outer surfaces thereof disposed outwardly from a conductor and above insulators and walls formed of electrically insulating material disposed between adjacent ones of the solder pads;
forming an adjacent chip stack element to include a substrate having two major surfaces, pads of a conductive seed layer arrayed along a plane of one of the major surfaces with outer surfaces thereof disposed outwardly from a conductor and above insulators, metallic posts disposed on top surfaces of the conductive seed layer pads, underbump metallurgy disposed on the metallic posts and solder joint material disposed within recesses cooperatively defined by the underbump metallurgy and walls surrounding the seed layer, the metallic posts and the underbump metallurgy; and
disposing the adjacent chip stack element relative to the chip stack element such that the solder joint material aligns with the solder pads of the chip stack element, wherein:
the walls of the chip stack element extend from uppermost surfaces of the insulators and are displaced from each of the adjacent ones of the solder pads, and
the walls of the adjacent chip stack element extend from uppermost surfaces of the insulators and contact each of the adjacent ones of the solder pads.
6. The method according to claim 5 , wherein the forming of the adjacent chip stack element comprises:
forming walls of electrically insulating material; and
forming top edge portions of the walls of the adjacent chip stack element to be narrower than top edge portions of the walls of the chip stack element.
7. The method according to claim 5 , wherein the solder pads occupy more than about 25-30% of an area of the one major surface.
8. The method according to claim 5 , wherein the solder pads have a pitch of about 100 microns or less.
9. The method according to claim 5 , further comprising forming the solder joint material into a solder joint occupying about 50% or more of the area of the chip stack.
10. The method according to claim 9 , wherein the forming comprises forming the solder joint and an adjacent solder joint with a pitch of about 100 microns or less.
11. The method according to claim 5 , further comprising disposing insulating walls proximate to each chip stack element.
12. A method of forming a chip stack, comprising:
forming a chip stack element to include a substrate having a major surface, solder pads arrayed along the major surface with outer surfaces thereof disposed outwardly from a conductor and above insulators and walls formed of electrically insulating material disposed between adjacent solder pads;
forming an adjacent chip stack element to include a substrate having a major surface, pads of a conductive seed layer arrayed along the major surface with outer surfaces thereof disposed outwardly from a conductor and above insulators, metallic posts disposed on top surfaces of the conductive seed layer pads and underbump metallurgy and solder joint material disposed on the metallic posts; and
disposing the adjacent chip stack element relative to the chip stack element such that the solder joint material aligns with the solder pads, wherein the forming of the adjacent chip stack element comprises:
forming walls of electrically insulating material between adjacent ones of the solder pads; and
forming top edge portions of the walls of the adjacent chip stack element to be narrower than top edge portions of the walls of the chip stack element, wherein:
the walls of the chip stack element extend from uppermost surfaces of the insulators and are displaced from each of the adjacent ones of the solder pads, and
the walls of the adjacent chip stack element extend from uppermost surfaces of the insulators and contact each of the adjacent ones of the solder pads.
13. The method according to claim 12 , wherein the solder pads occupy more than about 25-30% of an area of the major surface.
14. The method according to claim 12 , wherein the solder pads have a pitch of about 100 microns or less.
15. The method according to claim 12 , further comprising forming the solder joint material into a solder joint occupying about 50% or more of the area of the chip stack.
16. The method according to claim 15 , wherein the forming comprises forming the solder joint and an adjacent solder joint with a pitch of about 100 microns or less.
17. The method according to claim 15 , further comprising disposing insulating walls proximate to each chip stack element.