IP Library › Granted Patent US 8,994,454
Granted Patent B2
US 8,994,454 · App. 13/612,233 · Granted Mar 31, 2015

Amplifier circuit

Inventor: Tadamasa Murakami (Yokohama, JP)
Assignee: Samsung Electro-Mechanics Co., Ltd.
H03F1/02H03F1/223H03F1/523H03F1/56H03F3/189H03F2200/108H03F2200/18H03F2200/294H03F2200/444H03F2200/492
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Quick Facts
Patent No.
US 8,994,454
App. No.
13/612,233
Granted
Mar 31, 2015
Kind
B2
Abstract

According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.

Claims (17)

1. An amplifier circuit, comprising:

an input transistor;

a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and

a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage,

wherein the protective circuit includes:

a first MOS transistor that is diode-connected, and

a second MOS transistor disposed in parallel with the first MOS transistor and diode-connected in a reverse direction with respect to the first MOS transistor,

wherein a source of the first MOS transistor and a drain of the second MOS transistor are connected to the bias voltage, and

a body terminal of the first MOS transistor and a body terminal of the second MOS transistor are connected to a variable bias voltage.

2. An amplifier circuit, comprising:

an input transistor;

a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and

a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage,

wherein the protective circuit includes:

a first MOS transistor group including a plurality of MOS transistors disposed in series, respective MOS transistors being diode-connected in the same direction,

a second MOS transistor group disposed in parallel with the first MOS transistor group and including a plurality of MOS transistors disposed in series, respective MOS transistors being diode-connected in a reverse direction with respect to the respective MOS transistors included in the first MOS transistor group, and

a connection control unit controlling a short-circuit of sources and drains of the respective MOS transistors included in the first MOS transistor group and the second MOS transistor group.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2012
From: MURAKAMI, TADAMASA
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 028947/0477 →
Priority Claims (1)
JP 2011-255207 · Nov 22, 2011 · national
Continuity (1)
Related Publication 20130127544A1 · May 23, 2013