Oscillator arrangement for generating a clock signal
There is provided an oscillator arrangement for generating a clock signal. The oscillator arrangement comprises a current controlled oscillator, a frequency to voltage converter, and an operational amplifier. The oscillator arrangement is connectable to a supply voltage source. In one embodiment, the oscillator arrangement may achieve a stable clock frequency insensitive to supply and temperature variation with low current consumption and low area. This may be achieved by using Vref and Vout as input signals to the operational amplifier, both signals being directly derived from the supply voltage. In a further embodiment, a trimming resistor may be used in the frequency to voltage converter for adjusting the frequency.
1. An oscillator arrangement for generating a clock signal,
the oscillator arrangement comprising
a current controlled oscillator,
a frequency to voltage converter, and
an operational amplifier,
wherein the oscillator arrangement is connectable to a supply voltage source,
wherein the current controlled oscillator is adapted to generate a clock signal based on a control voltage signal, wherein the generated clock signal is supplied to the frequency to voltage converter,
wherein the frequency to voltage converter is adapted to generate an output voltage signal based on the generated clock signal and based on a supply voltage signal, said output voltage signal being directly derived from the supply voltage signal,
wherein the operational amplifier is adapted to receive the output voltage signal as a feedback signal at a first input terminal and to receive a reference voltage signal at a second input terminal, the reference voltage signal being directly derived from the supply voltage signal, such that variations in the supply voltage signal appear on the first input terminal and the second input terminal in the same amplitude and phase,
wherein the current controlled oscillator is adapted to be controlled based on an output signal of the operational amplifier, wherein the output signal of the operational amplifier provides the control voltage signal to the current controlled oscillator in order to control the frequency of the clock signal.
2. The oscillator arrangement according to claim 1 ,
further comprising an NMOS device, wherein the current controlled oscillator is connectable to the supply voltage source via the NMOS device, the NMOS device being controlled by the output signal of the operational amplifier.
3. The oscillator arrangement according to claim 2 ,
wherein the NMOS device is adapted to convert an input error voltage corresponding to the output signal of the operational amplifier into a current for controlling the current controlled oscillator.
4. The oscillator arrangement according to claim 1 ,
further comprising a voltage divider being adapted to generate the reference voltage from the supply voltage signal,
wherein the voltage divider is coupled between the voltage supply and the second input terminal of the operational amplifier.
5. The oscillator arrangement according to claim 1 ,
further comprising a level shifter unit being coupled between the current controlled oscillator and the frequency to voltage converter,
wherein the level shifter unit is adapted to convert the clock signal being generated by the current controlled oscillator into a rail-to-rail clock signal.
6. The oscillator arrangement according to claim 5 ,
wherein the frequency to voltage converter is adapted to generate the output voltage signal based on the rail-to-rail clock signal.
7. The oscillator arrangement according to claim 1 ,
wherein the frequency to voltage converter is implemented based on a switched capacitor resistor arrangement.
8. The oscillator arrangement according to claim 7 ,
wherein the frequency to voltage converter comprises a trimming resistor being part of the switched capacitor resistor arrangement, wherein the value of the trimming resistor is adjustable in order to adapt the frequency of the switched capacitor resistor arrangement.
9. The oscillator arrangement according to claim 8 ,
wherein the trimming resistor comprises a plurality of resistors, each resistor being controlled by a transistor.
10. The oscillator arrangement according to claim 1 ,
wherein the frequency to voltage converter comprises a logic unit, the logic unit being adapted to change a frequency operation mode of the oscillator arrangement.
11. A semiconductor device, the semiconductor device comprising an oscillator arrangement according to claim 1 .
12. A method of generating a clock signal,
the method comprising
generating, by a current controlled oscillator, a clock signal based on a control voltage signal, wherein the generated clock signal is supplied to a frequency to voltage converter,
generating, by the frequency to voltage converter, an output voltage signal based on the generated clock signal and based on a supply voltage signal, said output voltage signal being directly derived from the supply voltage signal,
receiving, by an operational amplifier, the output voltage signal as a feedback signal at a first input terminal and receiving, by the operational amplifier, a reference voltage signal at a second input terminal, the reference voltage signal being directly derived from the supply voltage signal, such that variations in the supply voltage signal appear on the first input terminal and the second input terminal in the same amplitude and phase,
controlling the current controlled oscillator based on an output signal of the operational amplifier, wherein the output signal of the operational amplifier provides the control voltage signal to the current controlled oscillator in order to control the frequency of the clock signal.
13. A non-transitory computer-readable medium, in which a computer program of generating an oscillation is stored, which computer program, when being executed by a processor, is adapted to carry out the method according to claim 12 .